Switching regulator and control circuit and control method thereof

Patent metadata

Field	Value
Publication number	US-10466732-B2
Application number	US-201916274162-A
Country	US
Kind code	B2
Filing date	Feb 12, 2019
Priority date	Mar 28, 2018
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

First claim

What is claimed is:

1. A switching regulator, configured to operably convert an input voltage to an output voltage, and comprising:
a power stage circuit including a high-side switch, a low-side switch, and an inductor coupled with one another, the power stage circuit being configured to operably convert the input voltage to the output voltage by operating the high-side switch and the low-side switch according to a high-side signal and a low-side signal respectively, and generate an inductor current flowing through the inductor; and
a control circuit, which is coupled to the power stage circuit, and includes:
a switching signal generation circuit, which is coupled to the power stage circuit, and is configured to operably generate the high-side signal and the low-side signal according to a command signal; and
an adjustment signal generation circuit, which is coupled to the power stage circuit and the switching signal generation circuit, and is configured to operably provide an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is electrically connected to an isolation region of the low-side switch;

wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level;
wherein the reverse recovery level is lower than the input voltage;
wherein the anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

2. The switching regulator of claim 1 , wherein the adjustment level is at the reverse recovery level in a reverse recovery time right after a first dead time, and is at the anti-latch-up level in a second dead time, wherein the first dead time is from when the high-side signal transits to a high-side inactive level to when the low-side signal transits to a low-side inactive level, and the second dead time is from when the low-side signal transits to a low-side inactive level to when the high-side signal transits to a high-side active level.

3. The switching regulator of claim 2 , wherein the adjustment signal generation circuit includes a logic circuit configured to generate the adjustment level which is inverse to the low-side signal.

4. The switching regulator of claim 2 , wherein the adjustment signal generation circuit includes a logic circuit configured to generate the adjustment level according to the high-side signal and the low-side signal, wherein the adjustment level is at the anti-latch-up level in the first dead time and the second dead time, and is at the reverse recovery level in a period other than the first dead time and the second dead time.

5. The switching regulator of claim 1 , wherein the adjustment signal generation circuit includes:
a negative current triggered clock generation circuit, configured to operably generate a negative current clock according to the inductor current, wherein the negative current clock signal is switched to an acknowledged level when the inductor current is a negative current;
a determination circuit, which is coupled to the negative current clock generation circuit, and is configured to operably generate a determination signal according to the negative current clock signal and a reference signal; and
a switching circuit, which is coupled to the determination circuit, and is configured to operably switch the adjustment level between the reverse recovery level and the anti-latch-up level according to the determination signal.

6. The switching regulator of claim 5 , wherein the determination circuit includes:
a low-pass filter, which is coupled to the negative current triggered clock generation circuit, and is configured to operably generate a comparison signal according to a duty ratio of the acknowledged level; and
a comparison circuit, which is coupled to the low-pass filter, and is configured to operably compare the comparison signal with the reference signal to generate the determination signal.

7. The switching regulator of claim 1 , wherein the reverse recovery level is a ground level or a low-side low level of the low-side signal, and the anti-latch-up level is a low-side high level of the low-side signal, a high-side high level of the high-side signal, the input voltage, or a phase voltage at a phase node among the high-side switch, the low-side switch and the inductor.

8. A control circuit of a switching regulator, wherein the switching regulator is configured to operably convert an input voltage to an output voltage, and include: a power stage circuit including a high-side switch, a low-side switch, and an inductor coupled with one another, the power stage circuit being configured to operably convert the input voltage to the output voltage by operating the high-side switch and the low-side switch according to a high-side signal and a low-side signal respectively, and generate an inductor current flowing through the inductor; and the control circuit, which is coupled to the power stage circuit; the control circuit comprising:
a switching signal generation circuit, which is coupled to the power stage circuit, and is configured to operably generate the high-side signal and the low-side signal according to a command signal; and
an adjustment signal generation circuit, which is coupled to the power stage circuit and the switching signal generation circuit, and is configured to operably provide an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is electrically connected to an isolation region of the low-side switch;
wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level;
wherein the reverse recovery level is lower than the input voltage;
wherein the anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

9. The control circuit of claim 8 , wherein the adjustment level is at the reverse recovery level in a reverse recovery time right after a first dead time, and is at the anti-latch-up level in a second dead time, wherein the first dead time is from when the high-side signal transits to a high-side inactive level to when the low-side signal transits to a low-side inactive level, and the second dead time is from when the low-side signal transits to a low-side inactive level to when the high-side signal transits to a high-side active level.

10. The control circuit of claim 9 , wherein the adjustment signal generation circuit includes a logic circuit configured to generate the adjustment level which is inverse to the low-side signal.

11. The control circuit of claim 9 , wherein the adjustment signal generation circuit includes a logic circuit configured to generate the adjustment level according to the high-side signal and the low-side signal, wherein the adjustment level is at the anti-latch-up level in the first dead time and the second dead time, and is at the reverse recovery level in a period other than the first dead time and the second dead time.

12. The control circuit of claim 8 , wherein the adjustment signal generation circuit includes:
a negative current triggered clock generation circuit, configured to operably generate a negative current clock according to the inductor current, wherein the negative current clock signal is switched to an acknowledged level when the inductor current is a negative current;
a determination circuit, which is coupled to the negative current clock generation circuit, and is configured to operably generate a determination signal according to the negative current clock signal and a reference signal; and
a switching circuit, which is coupled to the determination circuit, and is conf

Assignees

• Richtek Technology Corp

Inventors

• Chen Chien-Yu
• Huang Tsung-Yi
• Liao Ting-Wei

Classifications

• H02M3/1588

  comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02H9/048

  Anti-latching or quenching devices, i.e. bringing the protection device back to its normal state after a protection action · CPC title