Packet switch with reduced latency

Patent metadata

Field	Value
Publication number	US-10462075-B2
Application number	US-201715470940-A
Country	US
Kind code	B2
Filing date	Mar 28, 2017
Priority date	Aug 22, 2013
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

First claim

The invention claimed is:

1. A switching device, comprising:
a plurality of ports, which are configured to serve as ingress and egress ports so as to receive, queue, and transmit data packets from and to a network;
a switching core, which is coupled to transfer the data packets between the ingress and egress ports;
switching logic, which is coupled to maintain a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ingress ports,
to read the descriptors from the descriptor queue according to their turn in the descriptor queue, and
to instruct the switching core to transfer the queued data packets referred to by the read descriptors, between the plurality of ports; and

port logic associated with a specific one of the plurality of ports, configured to
determine, upon receipt of a data packet from the network at the specific port, whether the data packet meets a predefined criterion, and
responsive to determining that the data packet does not meet the predefined criterion:
signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue, and

responsive to identifying the data packet as meeting the predefined criterion, to:
signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue, and
convey a request to the switching logic, to instruct the switching core to begin to transfer the data packet immediately to an egress port, thereby upon grant of the request by the switching logic, the switching core transfers the data packet to the egress port, without dependence of the switching logic reading the descriptor corresponding to the data packet from the descriptor queue.

2. The device according to claim 1 ,
wherein the data packet is transferred to the egress port by instruction of the switching logic responsively to determining that the descriptor corresponding to the data packet advances to a head of the descriptor queue.

3. The device according to claim 1 , and
comprising a packet buffer, in which the plurality of ports queue the data packets for transfer by the switching core, and
wherein the switching core comprises:
a first input buffer coupled to receive the data packets from the packet buffer to be transferred in response to the queued descriptors;
a second input buffer coupled to receive the data packets from the packet buffer to be transferred in response to requests to begin to transfer the data packet immediately; and
a switch coupled to arbitrate between the first and second input buffers.

4. The device according to claim 3 ,
wherein the switching logic is coupled
to receive an indication of a fill status of the second input buffer and
to grant the request to begin to transfer the data packet immediately in response to emptying of the second input buffer.

5. The device according to claim 3 ,
wherein the packet buffer is centralized within the device.

6. The device according to claim 3 ,
wherein the packet buffer is distributed among the plurality of ports.

7. The device according to claim 1 ,
wherein the plurality of ports comprise a forwarding cache, which contains entries indicating respective egress ports for incoming data packets having header fields containing certain predefined values, and
wherein the port logic determines whether the data packet meets a predefined criterion based on finding for the data packet a corresponding entry in the forwarding cache.

8. The device according to claim 7 ,
wherein the port logic is further configured, upon determining the data packet does not meet the predefined criterion based on the data packet not being identified by the entries in the forwarding cache for immediate transfer to respective egress ports, to signal the switching logic to queue corresponding descriptors without requesting to begin to transfer the data packet immediately.

9. The device according to claim 1 ,
wherein the switching logic is configured to drop the descriptor corresponding to the data packet from the descriptor queue upon granting the request to transfer the data packet immediately to an egress port.

10. The device according to claim 1 ,
wherein the conveying of the request to the switching logic is a separate act from the signaling of the switching logic to place a descriptor corresponding to the data packet in the descriptor queue.

11. The device according to claim 1 ,
wherein the switching logic is configured to instruct the switching core to transfer the data packets to respective egress ports according to credits issued by the egress ports,
while dividing the credits for each egress port in accordance with a predefined distribution between first transfers of the data packets referred to by descriptors read from the queued descriptors and second transfers of the data packets in response to requests to bypass the descriptor queue.

12. The device according to claim 1 ,
wherein the data packet is transferred to the egress port through a same data path, regardless of whether the predefined criterion is met by the data packet.

13. The device according to claim 1 ,
wherein the data packet is transferred to the egress port through a same data path from the ingress port to the egress port, regardless of whether the conveyed request was granted or denied.

14. A method for communication, comprising:
coupling a switch, comprising a plurality of ports, which are configured to serve as ingress and egress ports, and a switching core, which is coupled to transfer data packets between the ingress and egress ports, to receive and transmit data packets from and to a network;
upon receiving a data packet from the network at a given ingress port, placing a corresponding descriptor in a descriptor queue, containing respective descriptors corresponding to data packets that have been received and queued by the ingress ports;
reading the descriptors from the descriptor queue, using switching logic in the switch, and
instructing the switching core to transfer the queued data packets referred to by the read descriptors, between the plurality of ports;
determining at the given ingress port, whether the data packet meets a predefined criterion;
upon identifying the received data packet at the given ingress port as meeting the predefined criterion, conveying a request to the switching logic, to instruct the switching core to begin to transfer the data packet immediately to an egress port; and
upon grant of the request by the switching logic, transferring the data packet to the egress port without dependence on the switching logic reading the descriptor corresponding to the data packet from the descriptor queue, and dropping the descriptor corresponding to the data packet from the descriptor queue.

15. The method according to claim 14 , and comprising,
upon refusal of the request, transferring the data packet to the egress port by instruction of the switching logic responsively to determining that the descriptor corresponding to the data packet from advances to a head of the descriptor queue.

16. The method according to claim 14 ,
wherein transferring the data packet comprises arbitrating between
a first input buffer coupled to receive the data packets to be transferred in response to the queued descriptors and
a second input buffer coupled to receive the data packets to be transferred in response to requests to transfer the data packet immediately to an egress port.

17. The method according to claim 16 ,
wherein transferring the data packe

Assignees

• Mellanox Technologies Ltd

Inventors

• Gabbay Freddy
• Bukshpan Ido
• Webman Alon
• Menes Miriam
• Elias George
• Katz Abramovich Noam

Classifications

• H04L49/9094

  Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element · CPC title

• H04L49/90 Primary

  Buffering arrangements · CPC title

• H04L49/901 Primary

  using storage descriptor, e.g. read or write pointers · CPC title