Hardware masked substitution box for the data encryption standard

Patent metadata

Field	Value
Publication number	US-10461925-B2
Application number	US-201715673284-A
Country	US
Kind code	B2
Filing date	Aug 9, 2017
Priority date	Sep 1, 2016
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

An integrated circuit may implement a masked substitution box that includes a counter that generates counter values. An input mask component may generate unmasked input values based on a combination of respective counter values and an input mask value. Furthermore, a substitution function component may receive the unmasked input values and may generate output values based on respective unmasked input values and a substitution function. An output mask component may generate masked output values based on a combination of respective output values and an output mask value. The masked output values may be stored at memory elements.

First claim

What is claimed is:

1. An integrated circuit comprising:
a counter to generate a plurality of counter values;
an input mask component to generate a plurality of unmasked input values, wherein an unmasked input value of the plurality of unmasked input values is based on a combination of a respective counter value of the plurality of counter values and an input mask value;
a substitution function component to receive the plurality of unmasked input values and to generate a plurality of output values, wherein an output value of the plurality of output values is based on a respective unmasked input value of the plurality of unmasked input values and a substitution function;
an output mask component to generate a plurality of masked output values, wherein a masked output value of the plurality of masked output values is based on a combination of a respective output value of the plurality of output values and an output mask value; and
a plurality of memory elements to store the plurality of masked output values.

2. The integrated circuit of claim 1 , wherein the integrated circuit corresponds to a substitution box, wherein input values of the substitution box are based on the counter values and output values of the substitution box are based on the output values that are generated based on the substitution function.

3. The integrated circuit of claim 1 , wherein the counter is a random counter that generates a sequence of random values in a random order.

4. The integrated circuit of claim 1 , further comprising:
a decoder to receive the counter values from the counter and to generate a plurality of decoded outputs, wherein a decoded output of the plurality of decoded outputs is used to enable one memory element of the plurality of memory elements to store a corresponding masked output value of the plurality of masked output values that has been generated by using a corresponding counter value of the plurality of counter values that was used to generate the corresponding masked output value.

5. The integrated circuit of claim 4 , further comprising:
a multiplexer coupled to the memory elements and to receive a selection signal and to select one of the masked output values stored at the memory elements as an output signal based on the selection signal matching a respective decoded output of the plurality of decoded outputs that was used to enable one of the memory elements.

Assignees

• Cryptography Res Inc

Inventors

• Baker Matthew Pond
• Trichina Elena
• Cioranesco Jean-Michel
• Hutter Michael

Classifications

• G06F21/755

  with measures against power attack · CPC title

• G06F21/556

  involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755) · CPC title

• H04L9/0618

  Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation · CPC title

• H04L9/003

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• H04L9/0631 Primary

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title