System and method for store fusion

Patent metadata

Field	Value
Publication number	US-10459726-B2
Application number	US-201715822515-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Nov 27, 2017
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Described herein is a system and method for store fusion that fuses small store operations into fewer, larger store operations. The system detects that a pair of adjacent operations are consecutive store operations, where the adjacent micro-operations refers to micro-operations flowing through adjacent dispatch slots and the consecutive store micro-operations refers to both of the adjacent micro-operations being store micro-operations. The consecutive store operations are then reviewed to determine if the data sizes are the same and if the store operation addresses are consecutive. The two store operations are then fused together to form one store operation with twice the data size and one store data HI operation.

First claim

What is claimed is:

1. A method for fusing store micro-operations, the method comprising:
determining whether adjacent micro-operations are consecutive store micro-operations, wherein the micro-operations are adjacent micro-operations if they flow through adjacent dispatch slots and adjacent micro-operations are consecutive store micro-operations if both of the adjacent micro-operations are store micro-operations;
if the adjacent micro-operations are consecutive store micro-operations:
determining whether the consecutive store micro-operations have a same data size;
determining whether the consecutive store micro-operations are accessing consecutive addresses; and
if the consecutive store micro-operations have the same data size and are accessing consecutive addresses, fusing the consecutive store micro-operations into a store micro-operation with twice the data size and a store data only micro-operation, wherein the store data only micro-operation suppresses a store queue and an address generation scheduler queue.

2. The method of claim 1 , further comprising:
setting a same store queue entry number for the store micro-operation with twice the data size and the store data only micro-operation.

3. The method of claim 2 , further comprising:
setting a micro-operation type in the store data only micro-operation to indicate that data in the store data only micro-operation is an upper data part with respect to the store micro-operation with twice the data size.

4. The method of claim 3 , further comprising:
sending at least one control bit to the store queue to facilitate shifting of the data when stored.

5. The method of claim 1 , wherein data in the store micro-operation with twice the data size is stored in a lower part of a store data field and data in the store data only micro-operation is stored in an upper part of the store data field.

6. The method of claim 1 , further comprising:
reviewing an addressing mode of each the consecutive micro-operations.

7. The method of claim 1 , wherein the consecutive store micro-operation having a lower address is converted to the store micro-operation with twice the data size.

8. The method of claim 7 , wherein the consecutive store micro-operation having a higher address is converted to the store data only micro-operation.

9. The method of claim 1 , wherein a store-retire indication is suppressed with respect to the store data only micro-operation.

10. The method of claim 1 , wherein an occurrence of an exception with respect to at least one of the store micro-operation with twice the data size and the store data only micro-operation results in re-execution of the adjacent micro-operations without fusing.

11. The method of claim 1 , further comprising:
setting a high store bit in a memory-renaming tracking structure for the store data only micro-operation; and
using the high store bit to determine store queue entry.

12. A processor for fusing store micro-operations, comprising:
a dispatch logic configured to dispatch micro-operations; and
a store fusion detection logic in communication with the dispatch logic, the store fusion detection logic configured to:
determine whether adjacent micro-operations are consecutive store micro-operations, wherein the micro-operations are adjacent micro-operations if they flow through adjacent dispatch slots and adjacent micro-operations are consecutive store micro-operations if both of the adjacent micro-operations are store micro-operations;
if the adjacent micro-operations are consecutive store micro-operations:
determine whether the consecutive store micro-operations have a same data size;
determine whether the consecutive store micro-operations are accessing consecutive addresses; and
if the consecutive store micro-operations have the same data size and are accessing consecutive addresses, fuse the consecutive store micro-operations into a store micro-operation with twice the data size and a store data only micro-operation, wherein the store data only micro-operation suppresses a store queue and an address generation scheduler queue.

13. The processor of claim 12 , wherein the dispatch logic and the store fusion detection logic are configured to set a same store queue entry number for the store micro-operation with twice the data size and the store data only micro-operation.

14. The processor of claim 13 , wherein the dispatch logic and the store fusion detection logic are configured to set a micro-operation type in the store data only micro-operation to indicate that data in the store data only micro-operation is an upper data part with respect to the store micro-operation with twice the data size.

15. The processor of claim 14 , further comprising:
an arithmetic logic unit in communication with the store queue, the arithmetic logic unit configured to send at least one control bit to the store queue to facilitate shifting of the data when stored.

16. The processor of claim 12 , wherein data in the store micro-operation with twice the data size is stored in a lower part of a store data field and data in the store data only micro-operation is stored in an upper part of the store data field.

17. The processor of claim 12 , wherein the consecutive store micro-operation having a lower address is converted to the store micro-operation with twice the data size and the consecutive store micro-operation having a higher address is converted to the store data only micro-operation.

18. The processor of claim 12 , wherein a store-retire indication is suppressed with respect to the store data only micro-operation and wherein an occurrence of an exception with respect to at least one of the store micro-operation with twice the data size and the store data only micro-operation results in re-execution of the adjacent micro-operations without fusing.

Assignees

• Advanced Micro Devices Inc

Inventors

• King John M

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F9/3017 Primary

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/4806

  Task transfer initiation or dispatching · CPC title

• G06F8/443

  Optimisation · CPC title