Memory device, and data processing method based on multi-layer RRAM crossbar array

Patent metadata

Field	Value
Publication number	US-10459724-B2
Application number	US-201816037767-A
Country	US
Kind code	B2
Filing date	Jul 17, 2018
Priority date	Jan 18, 2016
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R on or R off to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

First claim

What is claimed is:

1. A data processing apparatus comprising:
a control bus; and
multiple memory units connected by the control bus, each of the multiple memory units comprising a control circuit and a computation circuit,
wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar array and a format conversion circuit, the first RRAM crossbar array having multiple rows and multiple columns of memory cells, multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds, and outputs of the comparator circuits are connected to the format conversion circuit;
wherein the control circuit is connected to the control bus and configured to:
receive a computation instruction for performing a vector multiplication of vector A and vector B;
setting the memory cells in the first RRAM crossbar array such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B;
setting the word lines of the first RRAM crossbar array according to elements of vector A;

wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B;
the format conversion circuit being set up to convert the outputs of the comparator circuits into an output corresponding to a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

2. The data processing apparatus according to claim 1 , wherein the format conversion circuit comprises:
a second RRAM crossbar array connected to receive the outputs of the comparator circuits and configured to generate an output that corresponds to an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and
a third RRAM crossbar array connected to receive the output of the second RRAM crossbar array and configured to generate the output corresponding to the second binary number.

3. The data processing apparatus according to claim 2 , wherein
the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows×N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits;
the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j th word line in the N word lines is a voltage value corresponding to B j , a resistance value of a resistor in the j th row at the first RRAM crossbar array is a resistance value corresponding to A A , B j is the j th element of vector B, A J is the j th element of vector A, and a value of j ranges from 0 to N−1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2;
the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; and
the format conversion circuit receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and generates, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the format conversion circuit, voltage signals corresponding to the second binary number, wherein the second binary number is a binary representation of K.

4. The data processing apparatus according to claim 3 , wherein the j th comparator circuit in the N comparator circuits comprises a resistor R s of a constant resistance value and a comparator, one end of the resistor R s is connected to the j th bit line in the N bit lines and the comparator, the other end of the resistor R s is grounded, a voltage threshold of the j th comparator circuit is V r *g on *R s *(2j+1)/2, V r indicates a voltage value corresponding to a value 1, and g on indicates a reciprocal of R on .

5. The data processing apparatus according to claim 4 , wherein
the second RRAM crossbar array comprises a (2N−1) rows×N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array;
the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N−1 word lines, and performs a logic operation according to the voltage signal corresponding to the first computing result and a resistance value of a resistor at the second layer of RRAM crossbar array:

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Assignees

• Huawei Tech Co Ltd
• Univ Nanyang Tech

Inventors

• Yu Hao
• Wang Yuhao
• Zhao Junfeng
• Yang Wei
• Xiao Shihai
• Ni Leibin

Classifications

• G06N3/065

  Analogue means · CPC title

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/003 Primary

  Cell access · CPC title