Independent vector element order and memory byte order controls

Patent metadata

Field	Value
Publication number	US-10459700-B2
Application number	US-201615069704-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Mar 14, 2016
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Techniques are disclosed for managing vector element ordering. One technique includes setting one or more control bits that determine a vector element ordering and a vector element numbering, where the one or more control bits are stored in a machine status register or in a page table entry. The vector element ordering includes one of a big-endian mode and a little-endian mode, and the vector element numbering includes one of a big-endian mode and a little-endian mode. The technique includes reading the one or more control bits to determine a big-endian or a little-endian mode for the vector element ordering and for the vector element numbering. The technique also includes performing a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

First claim

What is claimed is:

1. A computer implemented method for managing vector element ordering, comprising:
setting a first control bit that determines a vector element ordering, wherein the single first control bit is stored in a page table entry, wherein the vector element ordering comprises one of a big-endian (BE) mode and a little-endian (LE) mode, wherein vector element ordering specifies how elements within a vector of elements are ordered, wherein each element in the vector includes a plurality of bytes;
setting a second control bit that determines a vector element numbering, wherein the second control bit is stored in the page table entry, wherein the vector element numbering comprises one of the BE mode and the LE mode, and wherein vector element numbering specifies how bytes of the plurality of bytes within an element are ordered;
reading the first control bit to determine which one of the BE mode and the LE mode for the vector element ordering is indicated;
reading the second control bit to determine which one of the BE mode and the LE mode for the vector element numbering is indicated; and
performing a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

2. The computer implemented method of claim 1 , wherein the first control bit and the second control bit are set by a machine instruction.

3. The computer implemented method of claim 2 , wherein an instruction sets the first control bit and the second control bit to a mode opposite an active mode.

4. The computer implemented method of claim 1 , wherein setting the first control bit and the second control bit further comprises setting the single control bit in the page table entry with an application-level instruction.

5. The computer implemented method of claim 1 , wherein setting the first control bit further comprises setting the first control bit by reading a register and copying a value for the first control bit to the page table entry.

6. A computer program product for managing vector element ordering, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by a processor to cause the processor to:
set a first control bit that determines a vector element ordering, wherein the first control bit is stored in a page table entry, wherein the vector element ordering comprises one of a big-endian (BE) mode and a little-endian (LE) mode, wherein vector element ordering specifies how elements within a vector of elements are ordered, and wherein each element of the elements within the vector includes a plurality of bytes;
set a second control bit that determines a vector element numbering, wherein the second control bit is stored in the page table entry, wherein the vector element numbering comprises one of the BE mode and the LE mode, and wherein vector element numbering specifies how bytes of the plurality of bytes within an element are ordered;
read the first control bit to determine which one of the BE mode and the LE mode for the vector element ordering is indicated;
read the second control bit to determine which one of the BE mode and the LE mode for the vector element numbering is indicated; and
perform a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

7. The computer program product of claim 6 , wherein the first control bit and the second control bit are set by a machine instruction.

8. The computer program product of claim 7 , wherein an instruction sets the first control bit and the second control bit to a mode opposite an active mode.

9. The computer program product of claim 6 , wherein setting the first control bit and the second control bit further comprises setting the first control bit and the second control bit in the machine status register with an application-level instruction.

10. The computer program product of claim 6 , wherein setting the first control bit and the second control bit further comprises setting the first control bit and the second control bit by reading a register and copying a value for the first control bit and the second control bit to the machine status register.

11. A system, comprising:
a processor; and
a memory storing a program, which, when executed on the processor, performs an operation for managing vector element ordering, the operation comprising:
setting a first control bit that determines a vector element ordering, wherein the first control bit is stored in a page table entry, wherein the vector element ordering comprises one of a big-endian (BE) mode and a little-endian (LE) mode, wherein vector element ordering specifies how elements within a vector of elements are ordered, wherein each element in the vector includes a plurality of bytes;
setting a second control bit that determines a vector element numbering, wherein the second control bit is stored in the page table entry, wherein the vector element numbering comprises one of the BE mode and the LE mode, and wherein vector element numbering specifies how bytes of the plurality of bytes within an element are ordered;
reading the first control bit to determine which one of the BE mode and the LE mode for the vector element ordering is indicated;
reading the second control bit to determine which one of the BE mode and the LE mode for the vector element numbering is indicated; and
performing a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

12. The system of claim 11 , wherein the first control bit and the second control bit are set by a machine instruction.

13. The system of claim 11 , wherein setting the first control bit and the second control bit further comprises setting the first control bit and the second control bit in the machine status register with an application-level instruction.

14. The system of claim 11 , wherein setting the first control bit and the second control bit further comprises setting the first control bit and the second control bit by reading a register and copying a value for the first control bit and the second control bit to the machine status register.

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Schmidt William J

Classifications

• G06F8/41 Primary

  Compilation · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title