Dual path sequential element to reduce toggles in data path

Patent metadata

Field	Value
Publication number	US-10459509-B2
Application number	US-201715483580-A
Country	US
Kind code	B2
Filing date	Apr 10, 2017
Priority date	Apr 10, 2017
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
switching logic, at least a portion of which is in hardware, to cause signals for a single data path of a processor to be directed to at least two separate data paths,
wherein at least one data path of the at least two separate data paths is to be power gated to reduce signal toggles in the at least one data path, wherein the single data path is to comprise a plurality of clock domains, wherein each of the at least two separate data paths is to comprise a single clock domain, wherein both of the at least two separate data paths are to operate at a same frequency that is lower than an operating frequency of the single data path.

2. The apparatus of claim 1 , wherein the switching logic is to comprise one or more latches or flip/flops.

3. The apparatus of claim 1 , further comprising a multiplexer to select between outputs of the at least two separate data paths.

4. The apparatus of claim 1 , comprising logic to determine which one of the at least two separate data paths to power gate.

5. The apparatus of claim 1 , wherein the processor is to comprise a Graphics Processing Unit (GPU) having one or more graphics processing cores.

6. The apparatus of claim 1 , wherein the processor is to comprise one or more processor cores.

7. The apparatus of claim 1 , wherein one or more of: the processor, the logic, and memory are on a single integrated circuit die.

8. The apparatus of claim 1 , wherein both of the at least two separate data paths are to operate at the same speed.

9. An apparatus comprising:
logic, at least a portion of which is in hardware, to cause signals for a single data path of a processor to be directed to at least two separate data paths,
wherein the at least two separate data paths are to omit one or more middle stage flops, wherein the single data path is to comprise a plurality of clock domains, wherein each of the at least two separate data paths is to comprise a single clock domain, wherein both of the at least two separate data paths are to operate at a same frequency that is lower than an operating frequency of the single data path.

10. The apparatus of claim 9 , wherein the at least two separate data paths are to be run at a first frequency value and the single data path is to be run at a second frequency value, wherein the first frequency value is half of the second frequency value.

11. The apparatus of claim 9 , wherein clock to output timing (Tco) or set up time (Tsu) penalty associated with the middle stage flops are to be reduced or eliminated in response to directing the signals to the at least two separate data paths.

12. The apparatus of claim 9 , further comprising a plurality of inverters to couple the at least two separate data paths to data input and data output ports.

13. The apparatus of claim 9 , wherein the processor is to comprise a Graphics Processing Unit (GPU) having one or more graphics processing cores.

14. The apparatus of claim 9 , wherein the processor is to comprise one or more processor cores.

15. The apparatus of claim 9 , wherein one or more of: the processor, the logic, and memory are on a single integrated circuit die.

16. An apparatus comprising:
logic, at least a portion of which is in hardware, to cause one or more of a plurality of flops in a data path of a processor to be bypassed in response to a determination that the processor is to run at a first frequency instead of a second frequency,
wherein the first frequency is lower than the second frequency, wherein the data path is to comprise a plurality of clock domains prior to bypassing the one or more flops, wherein the data path is to comprise a single clock domain after bypassing the one or more flops, wherein signals from a single data path of the processor are to be directed to at least two separate data paths, wherein both of the at least two separate data paths are to operate at a same frequency that is lower than an operating frequency of the single data path.

17. The apparatus of claim 16 , wherein the one or more of the flops that are to be bypassed are each coupled between a corresponding data input and a corresponding multiplexer.

18. The apparatus of claim 16 , wherein a first flop from the one or more of the flops is to be coupled between a first data input and a first multiplexer, wherein the first multiplexer is to select between the first data input and an output of the first flop in response to a control signal.

19. The apparatus of claim 16 , wherein a first flop from the one or more of the flops is to be coupled between a first data input and a first multiplexer, wherein the first multiplexer is to select between the first data input and an output of the first flop in response to a control signal, wherein the control signal is to be generated by a logic or micro-controller.

20. The apparatus of claim 16 , comprising logic to generate a signal to cause bypassing of the one or more flops.

21. The apparatus of claim 16 , further comprising a plurality of multiplexers coupled to cause bypassing of the one or more flops.

22. The apparatus of claim 16 , wherein the processor is to comprise a Graphics Processing Unit (GPU) having one or more graphics processing cores.

23. The apparatus of claim 16 , wherein the processor is to comprise one or more processor cores.

24. The apparatus of claim 16 , wherein one or more of: the processor, the logic, and memory are on a single integrated circuit die.

Assignees

• Intel Corp

Inventors

• Maiyuran Subramaniam
• Jahagirdar Sanjeev S
• Veernapu Kiran C
• Asperheim Eric J
• Koker Altug
• Vembu Balaji
• Ray Joydeep
• Appu Abhishek R

Classifications

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/329

  by task scheduling · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title