Configurable computing array comprising configurable computing elements

Patent metadata

Field	Value
Publication number	US-10456800-B2
Application number	US-201816121653-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Mar 5, 2016
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

To implement a complex math function, i.e. a math function with multiple input variables, a configurable computing array comprises at least an array of configurable computing elements. Each configurable computing element comprises at least a memory which stores a look-up table (LUT) for a math function with a single input variable.

First claim

What is claimed is:

1. A configurable computing array, comprising:
at least an array of configurable logic elements including a configurable logic element for selectively realizing a logic function from a logic library; and
at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises at least a first memory for storing at least a first portion of a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises at least a second memory for storing at least a second portion of a second LUT for a second math function;
whereby said configurable computing array realizes a third math function by programming said configurable logic elements and said configurable computing elements, wherein said third math function is a combination of at least said first and second math functions;
wherein each of said first and second math functions includes more operations than arithmetic operations included in said logic library.

2. The configurable computing array according to claim 1 , wherein said arithmetic operations included in said logic library consist of arithmetic addition and arithmetic subtraction.

3. The configurable computing array according to claim 1 , wherein said first math function has a first independent variable; said second math function has a second independent variable; and, said third math function has at least said first and second independent variables.

4. The configurable computing array according to claim 1 , further comprising a plurality of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library.

5. The configurable computing array according to claim 1 , wherein said first or second memory includes a three-dimensional memory (3D-M) array formed above said configurable logic element.

6. The configurable computing array according to claim 5 , wherein said 3D-M array at least partially covers said configurable logic element.

7. The configurable computing array according to claim 1 , wherein said first and second memories are electrically re-programmable, whereby said configurable computing elements can be re-configured to realize different math functions.

8. The configurable computing array according to claim 1 , wherein said array of configurable logic elements and said array of configurable computing elements are disposed on different physical levels.

9. The configurable computing array according to claim 8 , wherein said first or second memory at least partially overlaps with said configurable logic element.

10. The configurable computing array according to claim 1 , further comprising at least one multiplier.

11. A configurable computing array, comprising:
at least an array of configurable logic elements including a configurable logic element for selectively realizing a logic function from a logic library; and
at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises at least a first re-programmable memory for storing at least a first portion of a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises at least a second re-programmable memory for storing at least a second portion of a second LUT for a second math function;
whereby said configurable computing array realizes a third math function by programming said configurable logic elements and said configurable computing elements, wherein said third math function is a combination of at least said first and second math functions;
wherein each of said first and second math functions includes more operations than arithmetic operations included in said logic library.

12. The configurable computing array according to claim 11 , wherein said arithmetic operations included in said logic library consist of arithmetic addition and arithmetic subtraction.

13. The configurable computing array according to claim 11 , wherein said first math function has a first independent variable; said second math function has a second independent variable; and, said third math function has at least said first and second independent variables.

14. The configurable computing array according to claim 11 , further comprising a plurality of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library.

15. The configurable computing array according to claim 11 , wherein said first or second memory includes a three-dimensional memory (3D-M) array formed above said configurable logic element.

16. The configurable computing array according to claim 15 , wherein said 3D-M array at least partially covers said configurable logic element.

17. The configurable computing array according to claim 11 , wherein said array of configurable logic elements and said array of configurable computing elements are disposed on different physical levels.

18. The configurable computing array according to claim 17 , wherein said first memory and said configurable logic element at least partially overlap.

19. The configurable computing array according to claim 17 , wherein said second memory and said configurable logic element at least partially overlap.

20. The configurable computing array according to claim 11 , further comprising at least one multiplier.

Assignees

• Zhang Guobiao
• Hangzhou Haicun Information Tech Co Ltd

Inventors

• Zhang Guobiao

Classifications

• B05B11/1022

  actuated by pressure · CPC title

• B05B11/1097

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• B05B11/1073

  Springs · CPC title

• B65D47/2068

  in which the stem is lowered by the pressure of the contents and thereby opening the valve · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title