Multilayer ceramic substrate and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-10455699-B2
Application number	US-201615547882-A
Country	US
Kind code	B2
Filing date	Oct 17, 2016
Priority date	Oct 19, 2015
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A multilayer ceramic substrate includes: a plurality of ceramic layers 300a, 300b stacked together; a via hole 400a, 400b provided in each of the plurality of ceramic layers, the via holes of the plurality of ceramic layers being connected together in a layer stacking direction of the plurality of ceramic layers; a via wire 406a, 406b including an electrical conductor filled into each of the via holes; a first conductor 404a, 404b provided on an upper surface of at least one of the plurality of ceramic layers, the first conductor having an annular or partially annular shape surrounding the via wire; and a second conductor 403a, 403b including a first portion and a second portion, the first portion being located outside the first conductor on the upper surface of the at least one ceramic layer, the second portion overlying the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor, wherein a thickness of the first conductor 404a, 404b is greater than a thickness of the second conductor 403a, 403b.

First claim

The invention claimed is:

1. A multilayer ceramic substrate, comprising:
a plurality of ceramic layers stacked together;
a via hole provided in each of the plurality of ceramic layers, the via holes of the plurality of ceramic layers being connected together in a layer stacking direction of the plurality of ceramic layers;
a via wire including an electrical conductor filled into each of the via holes;
a first conductor provided on an upper surface of at least one of the plurality of ceramic layers, the first conductor having an annular or partially annular shape surrounding the via wire; and
a second conductor including a first portion and a second portion, the first portion being located outside the first conductor on the upper surface of the at least one ceramic layer, the second portion overlying and directly connected to the upper surface of the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor,
wherein a thickness of the first conductor is greater than a thickness of the second conductor,
wherein the via wire further includes a pad formed on at least one of the electrical-conductor-filled via holes of the at least one of the plurality of ceramic layers, the pad being electrically and physically separated from the first conductor,
wherein the second conductor has an opening,
wherein the second conductor is a solid electrode and the first portion of the second conductor extends from the first conductor to the end of the solid electrode,
wherein bottoms of both the first portion of the second conductor and the first conductor are directly on the at least one of the plurality of ceramic layers.

2. The multilayer ceramic substrate of claim 1 , wherein the opening of the second conductor is greater than the inner rim of the first conductor, and a rim of the opening is located inside an outer rim of the first conductor.

3. The multilayer ceramic substrate of claim 1 , wherein the via wire has the shape of a cylinder or a truncated cone.

4. The multilayer ceramic substrate of claim 3 , wherein the first conductor has the shape of a circular ring.

5. The multilayer ceramic substrate of claim 1 , wherein the second portion of the second conductor overlies the first conductor.

6. The multilayer ceramic substrate of claim 1 , wherein the second conductor is a ground electrode or an inner electrode of a capacitor.

7. The multilayer ceramic substrate of claim 1 , wherein each of the plurality of ceramic layers includes another via hole and another via wire which is formed by an electrical conductor filled into the another via hole, in the at least one ceramic layer, the another via wire is surrounded by the first conductor, and the another via wires of the plurality of ceramic layers are connected together.

8. The multilayer ceramic substrate of claim 1 , wherein bottoms of both the first portion of the second conductor and the first conductor are on the same plane.

9. A multilayer ceramic substrate, comprising:
a sintered ceramic body including a plurality of ceramic layers;
a via wire buried in the sintered ceramic body;
a first conductor located on a plane generally perpendicular to a center axis of the via wire, the first conductor having an annular or partially annular shape surrounding the via wire on the plane; and
a second conductor including a first portion and a second portion, the first portion being located outside the first conductor on the plane, the second portion overlying and directly connected to the upper surface of the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor,
wherein a thickness of the first conductor is greater than a thickness of the second conductor,
wherein the via wire further includes a pad formed on at least one of the electrical-conductor-filled via holes of at least one of the plurality of ceramic layers, the pad being electrically and physically separated from the first conductor,
wherein the second conductor has an opening,
wherein the second conductor is a solid electrode and the first portion of the second conductor extends from the first conductor to the end of the solid electrode,
wherein bottoms of both the first portion of the second conductor and the first conductor are directly on the at least one of the plurality of ceramic layers.

10. A method for manufacturing a multilayer ceramic substrate, comprising:
a first step of forming a via hole in each of a plurality of ceramic green sheets;
a second step of printing a conductor paste on an upper surface of each of the ceramic green sheets, thereby forming a via wire pattern in which the via hole is filled with the conductor paste and forming a first conductor pattern on an upper surface of at least one of the plurality of ceramic green sheets, the first conductor pattern having an annular or partially annular shape surrounding the via wire pattern;
a third step of printing a conductor paste on an upper surface of the at least one ceramic green sheet, thereby forming a second conductor pattern which has a smaller thickness than the first conductor pattern, the second conductor pattern including a first portion and a second portion, the first portion being located outside the first conductor on the upper surface of the at least one ceramic green sheet, the second portion overlying and directly connected to the upper surface of the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor; and
a fourth step of stacking up the plurality of ceramic green sheets and connecting the via wire patterns,
wherein the via wire further includes a pad formed on at least one of the electrical-conductor-filled via holes of the at least one of the plurality of ceramic green sheets, the pad being electrically and physically separated from the first conductor pattern,
wherein the second conductor pattern has an opening,
wherein the second conductor pattern is a solid electrode and the first portion of the second conductor pattern extends from the first conductor pattern to the end of the solid electrode, wherein bottoms of both the first portion of the second conductor and the first conductor are directly on the at least one of the plurality of ceramic green sheets.

11. The method of claim 10 , wherein
the first step includes forming the via hole by laser or a punch die, and
the via hole has the shape of a cylinder or a truncated cone.

12. The method of claim 10 further comprising, between the second step and the third step, a fifth step of reducing a height of the first conductor pattern.

13. The method of claim 12 , wherein the fifth step includes burying part of the first conductor pattern in the ceramic green sheet from the upper surface.

14. The method of claim 10 , wherein in the second step the via wire pattern and the first conductor pattern are printed using a same mask.

Assignees

• Hitachi Metals Ltd

Inventors

• Hayashi Kenji

Classifications

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K1/0222

  for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K2201/09809

  Coaxial layout · CPC title

• H05K1/116

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title