Imaging pixels with storage capacitors

Patent metadata

Field	Value
Publication number	US-10455162-B2
Application number	US-201815914122-A
Country	US
Kind code	B2
Filing date	Mar 7, 2018
Priority date	Jan 23, 2018
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

An image sensor may include an array of imaging pixels and row control circuitry. Each imaging pixel may include a photodiode, a floating diffusion region, a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, a dual conversion gain transistor coupled to the floating diffusion region, and a storage capacitor coupled to the dual conversion gain transistor. The capacitor may have a plate that receives a modulated control signal and the row control circuitry may be configured to modulate the control signal. To reduce image artifacts, the modulated control signal may be modulated low during the integration time of the pixel and may be modulated high during the high conversion gain readout time of the pixel.

First claim

What is claimed is:

1. An image sensor comprising:
an array of imaging pixels, wherein at least one of the imaging pixels comprises:
a photodiode;
a floating diffusion region;
a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region; and
a capacitor coupled to the floating diffusion region, wherein the capacitor has a plate that receives a control signal; and

row control circuitry, wherein the row control circuitry is configured to modulate the control signal and wherein the row control circuitry is configured to provide the control signal to a first imaging pixel of the array of imaging pixels at a first voltage during a reset period for the first imaging pixel and wherein the row control circuitry is configured to provide the control signal to the first imaging pixel at a second voltage that is less than the first voltage during an integration period for the first imaging pixel.

2. The image sensor defined in claim 1 , wherein the row control circuitry is configured to modulate the control signal between the first voltage, the second voltage, and a third voltage that is higher than the first voltage.

3. The image sensor defined in claim 2 , wherein the first voltage is a power supply voltage.

4. The image sensor defined in claim 2 , wherein the row control circuitry is configured to provide the control signal to the first imaging pixel at the third voltage during a high conversion gain readout period for the first imaging pixel and wherein the row control circuitry is configured to provide the control signal to the first imaging pixel at a fourth voltage that is less than the third voltage during a low conversion gain readout period for the first imaging pixel.

5. The image sensor defined in claim 4 , wherein the fourth voltage is different from the first voltage.

6. The image sensor defined in claim 1 , wherein the row control circuitry comprises a plurality of drivers and wherein each driver is configured to provide the control signal to a respective row of imaging pixels in the array of imaging pixels.

7. The image sensor defined in claim 1 , wherein each of the at least one imaging pixel comprises:
a transistor interposed between the capacitor and the floating diffusion region.

8. The image sensor defined in claim 7 , wherein each of the at least one imaging pixel comprises:
a source follower transistor, wherein the floating diffusion region is coupled to a gate of the source follower transistor; and
a reset transistor coupled between the floating diffusion region and a voltage supply that supplies a power supply voltage.

9. The image sensor defined in claim 8 , wherein the first voltage is equal to the power supply voltage.

10. The image sensor defined in claim 7 , wherein the transistor is a dual conversion gain transistor.

11. An image sensor comprising:
an array of imaging pixels, wherein at least one of the imaging pixels comprises:
a photodiode;
a floating diffusion region;
a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region; and
a capacitor coupled to the floating diffusion region, wherein the capacitor has a plate that is coupled to a control line; and

row control circuitry, wherein the row control circuitry is configured to provide a control signal to the plate of the capacitor through the control line and wherein the row control circuitry is configured to modulate the control signal between a power supply voltage, a first voltage that is less than the power supply voltage, and a second voltage that is higher than the power supply voltage.

12. The image sensor defined in claim 11 , wherein each of the at least one imaging pixel comprises:
a dual conversion gain transistor interposed between the capacitor and the floating diffusion region.

13. The image sensor defined in claim 11 , wherein the row control circuitry is configured to provide the control signal to a first imaging pixel of the array of imaging pixels at the power supply voltage during a reset period for the first imaging pixel, wherein the row control circuitry is configured to provide the control signal to the first imaging pixel at the first voltage during an integration period for the first imaging pixel, and wherein the row control circuitry is configured to provide the control signal to the first imaging pixel at the second voltage during a high conversion gain readout period for the first imaging pixel.

14. An image sensor comprising:
an array of imaging pixels that includes a first imaging pixel in a first row of imaging pixels, the first imaging pixel comprising:
a photodiode;
a floating diffusion region;
a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region; and
a capacitor that has a first plate coupled to the floating diffusion region and a second plate that is coupled to a control line; and

row control circuitry that includes a plurality of drivers, wherein a first driver of the plurality of drivers is coupled to the control line, wherein the first driver is configured to provide a control signal to the first row of imaging pixels using the control line, and wherein the first driver is configured to modulate the control signal between a first voltage and a second voltage that is less than the first voltage.

15. The image sensor defined in claim 14 , wherein the control line directly couples the second plate of the capacitor to the first driver.

16. The image sensor defined in claim 14 , wherein the first driver is configured to modulate the control signal between the first voltage, the second voltage, and a third voltage that is higher than the first voltage.

17. The image sensor defined in claim 16 , wherein the first voltage is a power supply voltage.

18. The image sensor defined in claim 14 , wherein the first driver is configured to provide the control signal to the first imaging pixel at the first voltage during a reset period for the first imaging pixel and wherein the first driver is configured to provide the control signal to the first imaging pixel at the second voltage during an integration period for the first imaging pixel.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Singh Gurvinder
• Oberoi Anirudh
• Balar Bharat
• Gurindagunta Sundaraiah

Classifications

• H04N25/59 Primary

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/65

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/627

  Detection or reduction of inverted contrast or eclipsing effects · CPC title

• H04N23/76 Primary

  by influencing the image signals · CPC title

• H04N25/63

  applied to dark current · CPC title