Memory optimization for nested hash operations

Patent metadata

Field	Value
Publication number	US-10454670-B2
Application number	US-201715603342-A
Country	US
Kind code	B2
Filing date	May 23, 2017
Priority date	Jun 10, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A first hash value is calculated by using a first input value that is stored in a first set of registers. The first hash value is then stored in a second set of registers. A second input value is stored in the first set of registers after calculating the first hash value. The second hash value is calculated based on the first hash value and the second input value. During the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.

First claim

What is claimed is:

1. A method comprising:
calculating a first hash value by using a first input value that is stored in a first set of registers;
storing the calculated first hash value in a second set of registers;
storing a second input value in the first set of registers after calculating the first hash value; and
calculating, by a processing device, a second hash value based on the first hash value and the second input value, wherein during the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers that stored the second input value when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.

2. The method of claim 1 , further comprising:
storing the second hash value in the second set of registers.

3. The method of claim 1 , wherein the first input value is stored in the first set of registers in a series of data blocks, and wherein the calculating of the first hash value by using the first input value corresponds to a shifting of one of the data blocks from a first register of the first set of registers to an adjacent register of the first set of registers.

4. The method of claim 1 , wherein data blocks of the first hash value are stored in the second set of registers, and wherein data blocks of the second input value are stored in the first set of registers, and wherein the calculating of the second hash value based on the first hash value and the second input value comprises:
shifting the data blocks of the second input value, wherein the shifting corresponds to a first data block of the data blocks of the second input value that is stored in a first register of the first set of registers being stored in a second register of the first set of registers, the second register being adjacent to the first register;
shifting the data blocks of the first hash value after the first hash value is shifted from the second set of registers to the portion of the first set of registers, wherein the shifting corresponds to a first data block of the data blocks of the first hash value that is stored in a first register of the portion of the first set of registers being stored in a second register of the portion of the first set of registers, the second register of the portion being adjacent to the first register of the portion.

5. The method of claim 1 , wherein the first input value corresponds to an input message and a key associated with a first padding data, and wherein the second input value corresponds to the key associated with a second padding data.

6. The method of claim 1 , wherein the calculating of the first hash value corresponds to a first hash operation and the calculating of the second hash value corresponds to a second hash operation, and wherein the first hash operation and the second hash operation correspond to nested hash operations.

7. The method of claim 1 , further comprising:
identifying that the calculating of the second hash value has reached a state where the portion of the first set of registers are not used to store data blocks associated with the second input value; and
in response to identifying that the calculating of the second hash value has reached the state, providing an enable signal to shift the first hash value from the second set of registers to the portion of the first set of registers.

8. A system comprising:
a first set of registers;
a second set of registers; and
a processing device, operatively coupled with the first and second set of registers, to:
calculate a first hash value by using a first input value that is stored in the first set of registers;
store the calculated first hash value in the second set of registers;
store a second input value in the first set of registers after calculating the first hash value; and
calculate a second hash value based on the first hash value and the second input value, wherein during the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers that stored the second input value when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.

9. The system of claim 8 , wherein the processing device is further to:
store the second hash value in the second set of registers.

10. The system of claim 8 , wherein the first input value is stored in the first set of registers in a series of data blocks, and wherein the calculating of the first hash value by using the first input value corresponds to a shifting of one of the data blocks from a first register of the first set of registers to an adjacent register of the first set of registers.

11. The system of claim 8 , wherein data blocks of the first hash value are stored in the second set of registers, and wherein data blocks of the second input value are stored in the first set of registers, and wherein the calculating of the second hash value based on the first hash value and the second input value comprises:
shifting the data blocks of the second input value, wherein the shifting corresponds to a first data block of the data blocks of the second input value that is stored in a first register of the first set of registers being stored in a second register of the first set of registers, the second register being adjacent to the first register;
shifting the data blocks of the first hash value after the first hash value is shifted from the second set of registers to the portion of the first set of registers, wherein the shifting corresponds to a first data block of the data blocks of the first hash value that is stored in a first register of the portion of the first set of registers being stored in a second register of the portion of the first set of registers, the second register of the portion being adjacent to the first register of the portion.

12. The system of claim 8 , wherein the first input value corresponds to an input message and a key associated with a first padding data, and wherein the second input value corresponds to the key associated with a second padding data.

13. The system of claim 8 , wherein the calculating of the first hash value corresponds to a first hash operation and the calculating of the second hash value corresponds to a second hash operation, and wherein the first hash operation and the second hash operation correspond to nested hash operations.

14. The system of claim 8 , wherein the processing device is further to:
identify that the calculating of the second hash value has reached a state where the portion of the first set of registers are not used to store data blocks associated with the second input value; and
in response to identifying that the calculating of the second hash value has reached the state, provide an enable signal to shift the first hash value from the second set of registers to the portion of the first set of registers.

15. A non-transitory computer readable medium comprising data that, when accessed by a processing device, cause the processing device to perform operations comprising:
calculating a first hash value by using a first input value that is stored in a first set of registers;
storing the calculated first hash value in a second set of registers;
storing a second input value in the first set of registers after calculating the first hash value; and
calculating a second hash value based on the first hash value and the second input value, wher

Assignees

• Cryptography Res Inc

Inventors

• Hutter Michael
• Baker Matthew Pond

Classifications

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/0643 Primary

  Hash functions, e.g. MD5, SHA, HMAC or f9 MAC · CPC title