Hybrid-controlled clock generation

Patent metadata

Field	Value
Publication number	US-10454665-B2
Application number	US-201815924066-A
Country	US
Kind code	B2
Filing date	Mar 16, 2018
Priority date	Mar 16, 2018
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.

First claim

What is claimed is:

1. An apparatus comprising:
an analog control circuit;
a digital control circuit;
an oscillator circuit;
a transistor array comprising multiple transistors coupled together in parallel between a supply voltage and the oscillator circuit; and
a selection circuit including a first input coupled to the analog control circuit, a second input coupled to the digital control circuit, and an output coupled to the transistor array, the selection circuit configured to:
obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit; and
connect, based on the selection signal, the analog control circuit or the digital control circuit to one or more gates of the multiple transistors of the transistor array.

2. The apparatus of claim 1 , wherein:
the transistor array is configured to generate, based on a control voltage, a bias current using one or more of the multiple transistors;
the analog control circuit is configured to generate an analog control signal that provides the control voltage responsive to the analog control circuit being connected to the one or more gates of the multiple transistors via the selection circuit;
the digital control circuit is configured to generate a digital control signal that provides the control voltage responsive to the digital control circuit being connected to the one or more gates of the multiple transistors via the selection circuit; and
the oscillator circuit is configured to generate a clock signal based on the bias current.

3. The apparatus of claim 2 , wherein:
the analog control circuit comprises an automatic gain control circuit coupled to the oscillator circuit, the automatic gain control circuit configured to:
monitor an amplitude of the clock signal; and
adjust the bias current via the analog control signal based on the amplitude of the clock signal; and

the digital control circuit comprises a register, the register configured to:
obtain a digital control adjustment signal from a processor; and
adjust the bias current via the digital control signal based on the digital control adjustment signal.

4. The apparatus of claim 2 , wherein:
the analog control signal comprises multiple analog control signals;
the analog control circuit is configured to use the multiple analog control signals to respectively set control voltages at two or more gates of the multiple transistors responsive to being connected to the two or more gates of the multiple transistors via the selection circuit;
the digital control signal comprises multiple digital control signals; and
the digital control circuit is configured to use the multiple digital control signals to respectively set the control voltages at the two or more gates of the multiple transistors responsive to being connected to the two or more gates of the multiple transistors via the selection circuit.

5. The apparatus of claim 4 , wherein:
a quantity of the multiple analog control signals and a quantity of the multiple digital control signals are both equal to a quantity of the multiple transistors; and
the selection circuit comprises a multiplexer, the multiplexer includes a selection input, the multiplexer configured to:
obtain the selection signal from a processor via the selection input;
obtain the multiple analog control signals via the first input;
obtain the multiple digital control signals via the second input; and
respectively provide, via the output, the multiple analog control signals or the multiple digital control signals to the two or more gates of the multiple transistors based on the selection signal.

6. The apparatus of claim 2 , wherein:
the multiple transistors include a first set of transistors respectively coupled in series with a second set of transistors to form multiple branches, the multiple branches coupled in parallel with each other;
the analog control signal comprises a single analog control signal that provides a first control voltage as the control voltage;
the digital control signal comprises multiple digital control signals that respectively provide second control voltages as the control voltage; and
the selection circuit is configured to selectively:
provide the first control voltage to one or more gates of the first set of transistors via the single analog control signal; or
provide the second control voltages respectively to two or more gates of the second set of transistors via the multiple digital control signals.

7. The apparatus of claim 6 , wherein the selection circuit is configured to:
based on the analog control circuit being connected to the one or more gates of the first set of transistors, connect one or more gates of the second set of transistors to a reference voltage; or
based on the digital control circuit being connected to the two or more gates of the second set of transistors, connect the two or more gates of the first set of transistors to the reference voltage.

8. The apparatus of claim 2 , wherein:
at least a portion of the multiple transistors are configured to operate in a saturation region based on the analog control signal; and
at least another portion of the multiple transistors are configured to operate in a linear region based on the digital control signal.

9. The apparatus of claim 1 , wherein the multiple transistors comprise multiple p-channel metal-oxide-semiconductor field-effect transistors having respective sources coupled to the supply voltage and respective drains coupled to the oscillator circuit.

10. The apparatus of claim 1 , wherein the oscillator circuit includes a single quartz crystal.

11. The apparatus of claim 1 , further comprising a clock generator, the clock generator including the analog control circuit, the digital control circuit, the transistor array, the oscillator circuit, and the selection circuit.

12. An apparatus comprising:
an analog control circuit;
a digital control circuit;
an oscillator circuit configured to generate a clock signal based on a bias current;
a transistor array configured to generate the bias current based on a control voltage, the transistor array comprising multiple transistors coupled together in parallel between a supply voltage and the oscillator circuit; and
selection means for providing the control voltage to bias the transistor array; the selection means coupled to the analog control circuit, the digital control circuit, and the transistor array; the selection means configured to connect the analog control circuit or the digital control circuit to one or more gates of the multiple transistors of the transistor array based on a selection signal.

13. The apparatus of claim 12 , wherein:
the analog control circuit is configured to generate an analog control signal that provides the control voltage responsive to the analog control circuit being connected to the one or more gates of the multiple transistors via the selection means; and
the digital control circuit is configured to generate a digital control signal that provides the control voltage responsive to the digital control circuit being connected to the one or more gates of the multiple transistors via the selection means.

14. The apparatus of claim 12 , wherein:
the selection means includes a selection input; and
the selection means is configured to obtain the selection signal from a processor via the selection input.

15. The apparatus of claim 12 , wherein:
the selection means is configured to:
connect the analog control circuit to a portion of the gates of the multiple transistors; or

Assignees

• Qualcomm Inc

Inventors

• Iguchi Shunta
• Deligoz Ilker
• Farias Michael Naone

Classifications

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03L5/00

  Automatic control of voltage, current, or power · CPC title

• H03B5/36 Primary

  active element in amplifier being semiconductor device ({H03B5/323, H03B5/326} , H03B5/38 take precedence) · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04B1/40

  Circuits · CPC title