Communication circuit including a transmitter

Patent metadata

Field	Value
Publication number	US-10454509-B2
Application number	US-201815962865-A
Country	US
Kind code	B2
Filing date	Apr 25, 2018
Priority date	Mar 13, 2018
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

First claim

What is claimed is:

1. A communication circuit comprising:
a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate a first plurality of baseband signals;
a second pair of DACs coupled to an input of a second mixer and configured to generate a second plurality of baseband signals, the second plurality of baseband signals shifted in phase relative to the first plurality of baseband signals;
a first pair of baseband filters (BBFs) coupled to the first pair of DACs; and
a second pair of baseband filters coupled to the second pair of DACs, wherein each baseband filter comprises a common mode feedback loop.

2. The communication circuit of claim 1 , in which the first plurality of baseband signals are shifted in phase by 45 degrees relative to the second plurality of baseband signals.

3. The communication circuit of claim 1 , in which the first plurality of baseband signals and the second plurality of baseband signals comprise analog signals.

4. The communication circuit of claim 1 , in which the first plurality of baseband signals and the second plurality of baseband signals comprise differential signals.

5. The communication circuit of claim 1 , in which each baseband filter comprises a resistor-capacitor (RC) filter.

6. The communication circuit of claim 1 , further comprising:
a first phase generator coupled to an input of a first one of the second pair of DACs and configured to receive baseband data comprising an in-phase (I) component and a quadrature-phase (Q) component and configured to generate a first new component of baseband data from both of the received I and Q components; and
a second phase generator coupled to an input of second one of the second pair of DACs and configured to receive the baseband data comprising the I component and the Q component and configured to generate a second new component of baseband data from both of the received I and Q components, the first new component differing from the second new component.

7. The communication circuit of claim 6 , in which the baseband data, the first new component of baseband data, and the second new component of baseband data comprise digital data.

8. The communication circuit of claim 6 , in which the first new component of baseband data is shifted by 45 degrees relative to the I component, and the second new component of baseband data is shifted in phase by 45 degrees relative to the Q component.

9. The communication circuit of claim 1 , in which:
the first mixer comprises a first pair of mixers configured to receive the first plurality of baseband signals and a first plurality of local oscillator (LO) signals; and
the second mixer comprises a second pair of mixers configured to receive the second plurality of baseband signals and a second plurality of LO signals, the second plurality of baseband signals shifted in phase relative to the first plurality of baseband signals, and the second plurality of LO signals shifted in phase relative to the first plurality of LO signals, the first pair of mixers and the second pair of mixers configured to generate voltage mode outputs.

10. The communication circuit of claim 9 , in which outputs of the mixers are coupled to each other through a short duty cycle local oscillator (LO) pulse.

11. The communication circuit of claim 1 , in which in-phase (I) signals and quadrature-phase (Q) signals input to the first pair of DACs are each clocked by a rising edge of a sampling clock signal.

12. The communication circuit of claim 11 , in which in-phase (I) signals and quadrature-phase (Q) signals input to the second pair of DACs are each clocked by a falling edge of the sampling clock signal.

13. A method for communication, comprising:
generating a first plurality of baseband signals with a first pair of digital-to-analog converters (DACs); and
generating a second plurality of baseband signals with a second pair of DACs, the second plurality of baseband signals shifted in phase relative to the first plurality of baseband signals
wherein in-phase (I) signals and quadrature-phase (Q) signals input to the first pair of DACs are each clocked by a rising edge of a sampling clock signal.

14. The method of claim 13 , in which the first plurality of baseband signals are shifted in phase by 45 degrees relative to the second plurality of baseband signals.

15. The method of claim 13 , in which the first plurality of baseband signals and the second plurality of baseband signals comprise analog signals.

16. The method of claim 13 , in which the first plurality of baseband signals and the second plurality of baseband signals comprise differential signals.

17. The method of claim 13 , further comprising:
receiving baseband data comprising an in-phase (I) component and a quadrature-phase (Q) component;
generating a first new component of baseband data from both of the received I and Q components; and
generating a second new component of baseband data from both of the received I and Q components.

18. The method of claim 17 , in which the received baseband data, the first new component of baseband data, and the second new component of baseband data comprise digital data.

19. The method of claim 17 , in which the first new component of baseband data is shifted by 45 degrees relative to the I component, and the second new component of baseband data is shifted in phase by 45 degrees relative to the Q component.

20. The method of claim 13 , in which in-phase (I) signals and quadrature-phase (Q) signals input to the second pair of DACs are each clocked by a falling edge of the sampling clock signal.

21. A communication circuit comprising:
first means for generating a first plurality of baseband signals; and
second means for generating a second plurality of baseband signals, the second plurality of baseband signals shifted in phase relative to the first plurality of baseband signals, wherein:
in-phase (I) signals and quadrature-phase (Q) signals input to the first means are each clocked by a rising edge of a sampling clock signal; and
in-phase (I) signals and quadrature-phase (Q) signals input to the second means are each clocked by a falling edge of the sampling clock signal.

Assignees

• Qualcomm Inc

Inventors

• Asuri Bhushan Shanti
• Thiagarajan Krishnaswamy
• Swaminathan Ashok
• Mehdizad Taleie Shahin
• Chang Yen-Wei
• Panikkath Vinod
• Vora Sameer Vasantlal
• Mittal Ayush
• Biswas Tonmoy
• Hwu Sy-Chyuan
• Tang Zhilong
• Chamas Ibrahim
• Lai Ping Wing
• Sedighi Behnam
• Seo Dongwon
• Saputra Nitz

Classifications

• H03F2203/45051

  Two or more differential amplifiers cascade coupled · CPC title

• H03F3/45636

  by using feedback means (H03F3/45744 takes precedence) · CPC title

• H04B1/0032

  with analogue quadrature frequency conversion to and from the baseband (quadrature modulators and demodulators per se H03D3/007, H03C3/40) · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H04B1/30

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title