Apparatus and method for mapping binary to ternary and its reverse

Patent metadata

Field	Value
Publication number	US-10454495-B2
Application number	US-201414490307-A
Country	US
Kind code	B2
Filing date	Sep 18, 2014
Priority date	Sep 18, 2014
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

First claim

We claim:

1. An apparatus comprising:
a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits, wherein the first LUT is implemented in hardware as logic gates in a range of about 100 gates, and wherein the first LUT includes numbers that represent:

Binary Value
Ternary Representation

 2 0 = 1
1

 2 1 = 2
2

 2 2 = 4
11

 2 3 = 8
22

 2 4 = 16
121

 2 5 = 32
1012

. . .

2 18 = 262,144
111022121001

and
a first logic communicatively coupled to the first LUT, wherein the first logic is to receive a binary input and is to convert the binary input to a ternary output according to the first LUT, and wherein the conversion to the ternary output is unique and lossless.

2. The apparatus of claim 1 comprises:
a second LUT having a mapping of 12 ternary trits to 19 binary bits; and
a second logic to receive the ternary output and to convert it to a binary output according to the second LUT, wherein the conversion to the binary output is unique and lossless.

3. The apparatus of claim 1 , wherein the first LUT includes 19 entries corresponding to the power of 2 values in ternary for power of 2 from 0 to 18.

4. The apparatus of claim 2 , wherein the second LUT includes 12 entries corresponding to the power of 3 values in binary for power of 3 from 0 to 11.

5. The apparatus of claim 1 , wherein the first logic comprises: logic to initialize the ternary output to zero.

6. The apparatus of claim 5 , wherein the first logic comprises: logic to determine the location of ones in binary input.

7. The apparatus of claim 6 , wherein the binary input has 19 binary bits.

8. The apparatus of claim 6 , wherein the first logic comprises logic to detect a one in the binary input.

9. The apparatus of claim 6 , wherein the first logic comprises: logic to read from the first LUT a ternary representation according to a corresponding location of one from the location of ones in the binary input.

10. The apparatus of claim 9 , wherein the first logic comprises an adder to add, in ternary domain, the ternary representation to the initialized ternary output to generate the ternary output.

11. The apparatus of claim 10 , wherein the ternary output is a 12 ternary symbol value.

12. The apparatus of claim 2 , wherein the second logic comprises: logic to read the ternary output and to initialize the binary output to zero.

13. The apparatus of claim 12 , wherein the second logic comprises:
logic to determine location of ones in the 12 ternary trits of the ternary output;
logic to read from the second LUT a binary representation according to a corresponding location of one from the location of ones in the ternary input; and
an adder to add, in binary domain, the binary representation to the initialized binary output to generate the binary output.

14. A system comprising:
a non-volatile memory;
a processor coupled to the non-volatile memory, the processor including:
a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; wherein the first LUT includes numbers that represent:

Binary Value
Ternary Representation

 2 0 = 1
1

 2 1 = 2
2

 2 2 = 4
11

 2 3 = 8
22

 2 4 = 16
121

 2 5 = 32
1012

. . .

2 18 = 262,144
111022121001

a second LUT having a mapping of 12 ternary trits to 19 binary bits;

wherein the second LUT includes numbers that represent:

Ternary Value
Binary Representation

 3 0 = 1
1

 3 1 = 3
11

 3 2 = 9
1001

 3 3 = 27
11011

 3 4 = 81
1010001

 3 5 = 243
11110011

. . .

3 11 = 177,174
101011010000010110

a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT, wherein the conversion to the ternary output is

Assignees

• Intel Corp

Inventors

• Motwani Ravi H
• Kalavade Pranav

Classifications

• H03M7/02 Primary

  Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word · CPC title

• H03M5/16

  the pulses having three levels · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title