Crystal driver circuit configurable for daisy chaining

Patent metadata

Field	Value
Publication number	US-10454420-B2
Application number	US-201715645684-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Jun 30, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A crystal driver integrated circuit configurable for daisy chaining including an amplifier core, an input pin and an output pin, and a controller that operates the amplifier core in any one of multiple operating modes. The operating modes include an oscillator mode for driving an external crystal coupled between the input and output pins to generate an oscillation signal at a target frequency, and an amplifier mode that amplifies an external oscillating signal provided to the input pin to provide an amplified oscillation signal on the output pin. The amplifier core includes a controllable current source that provides a core bias current to an amplifier having a level that is adjusted depending upon the operating mode and desired amplitude. The operating modes may include a bypass mode in which the amplifier core is disabled. The amplifier may be implemented as either an PMOS amplifier or an NMOS amplifier.

First claim

The invention claimed is:

1. A crystal driver integrated circuit, comprising:
an amplifier core, comprising:
a controllable current source having an output that provides a core bias current to a source node; and
an amplifier coupled between said source node and a reference node, having an input coupled to an amplifier input node and having an output coupled to an amplifier output node;

an input pin coupled to said amplifier input node and an output pin coupled to said amplifier output node; and
a controller that operates said amplifier core in any one of a plurality of operating modes based on a mode input, including an oscillator mode for driving an external crystal coupled between said input and output pins to generate an oscillation signal at a target frequency, including an amplifier mode that amplifies an external oscillating signal provided to said input pin to provide an amplified oscillation signal on said output pin, and including a bypass mode in which said controller disables said amplifier core.

2. The crystal driver integrated circuit of claim 1 , wherein said controller adjusts said current source to provide said core bias current so that said oscillation signal on said input pin has a first target amplitude during said oscillator mode, and wherein said controller adjusts said current source to provide said core bias current so that said amplified oscillation signal on said output pin has a second target amplitude during said amplifier mode.

3. The crystal driver integrated circuit of claim 2 , wherein said first and second target amplitudes are equal.

4. The crystal driver integrated circuit of claim 1 , wherein during said amplifier mode, said controller disables a first tune capacitor coupled to said amplifier output node and disables a second tune capacitor coupled to said amplifier input node.

5. The crystal driver integrated circuit of claim 1 , wherein said controller disables a tune capacitor coupled to said amplifier input node during said bypass mode.

6. The crystal driver integrated circuit of claim 1 , wherein said inverting amplifier comprises one of a PMOS amplifier and an NMOS amplifier.

7. The crystal driver integrated circuit of claim 1 , further comprising:
a memory that stores a first and second values; and
wherein said controller uses said first value to adjust said current source to set said core bias current during said oscillator mode, and uses said second value to adjust said current source to set said core bias current during said amplifier mode.

8. The crystal driver integrated circuit of claim 1 , further comprising:
a select circuit having an output that conveys a selected one of said amplifier input node and said amplifier output node based on a select input;
a level detector having an input coupled to said output of said select circuit and having an output providing a level value to said controller; and
wherein said controller controls said select input of said select circuit to select said amplifier input node to set a level of said core bias current for said oscillator mode, and controls said select input of said select circuit to select said amplifier output node to set a level of said core bias current for said amplifier mode.

9. A crystal driver daisy chain configuration, comprising:
a plurality of crystal driver integrated circuits coupled in a daisy chain configuration, each comprising:
an amplifier core, comprising:
a controllable current source having an output that provides a core bias current to a source node; and
an amplifier coupled between said source node and a reference node, having an input coupled to an amplifier input node and having an output coupled to an amplifier output node;

an input pin coupled to said amplifier input node and an output pin coupled to said amplifier output node; and
a controller that operates said amplifier core in any one of a plurality of operating modes based on a mode input, including an oscillator mode for driving an external crystal coupled between said input and output pins to generate an oscillation signal at a resonant frequency, and an amplifier mode that amplifies an external oscillating signal provided to said input pin to provide an amplified oscillation signal on said output pin; and

wherein at least one of said plurality of crystal driver integrated circuits is operated in said amplifier mode having an output pin providing an amplified oscillation signal to an input pin of at least one other one of said plurality of crystal driver integrated circuits.

10. The crystal driver daisy chain configuration of claim 9 , further comprising a crystal oscillator providing an oscillation signal to an input pin of one of said plurality of crystal driver integrated circuits operated in said amplifier mode.

11. The crystal driver daisy chain configuration of claim 10 , wherein said crystal oscillator comprises a first one of said plurality of crystal driver integrated circuits operated in said oscillator mode having an input pin providing said oscillation signal.

12. The crystal driver daisy chain configuration of claim 9 , wherein:
a first one of said plurality of crystal driver integrated circuits is operated in said amplifier mode having an input pin receiving an external oscillation signal and having an output pin providing a first amplified oscillation signal; and
wherein a second one of said plurality of crystal driver integrated circuits is operated in said amplifier mode having an input pin coupled to said output pin of said first one and having an output pin providing a second amplified oscillation signal.

13. The crystal driver daisy chain configuration of claim 9 , wherein each of said plurality of crystal driver integrated circuits are operated in said amplifier mode, including a first one having an input pin receiving an external oscillating signal and a last one receiving an amplified oscillation signal.

14. The crystal driver daisy chain configuration of claim 9 , wherein said plurality of modes includes a bypass mode in which said controller disables an amplifier core of a crystal driver integrated circuit operated in said bypass mode.

15. The crystal driver daisy chain configuration of claim 14 , wherein:
a first one of said plurality of crystal driver integrated circuits is operated in said amplifier mode having an input pin receiving an external oscillation signal and having an output pin providing an amplified oscillation signal; and
wherein a second one of said plurality of crystal driver integrated circuits is operated in said bypass mode having an input pin coupled to said output pin of said first one for receiving said amplified oscillation signal.

16. The crystal driver daisy chain configuration of claim 15 , wherein said plurality of crystal driver integrated circuits includes at least one additional crystal driver integrated circuit operated in said bypass mode having an input pin coupled to said output pin of said first one for receiving said amplified oscillation signal.

17. The crystal driver daisy chain configuration of claim 14 , wherein:
a first one of said plurality of crystal driver integrated circuits is operated in said amplifier mode having an input pin receiving an external oscillation signal and having an output pin providing a first amplified oscillation signal;
wherein a second one of said plurality of crystal driver integrated circuits is operated in said bypass mode having an input pin coupled to said output pin of said first one for receiving said first amplified oscillation signal; and
wherein a third one of said pluralit

Assignees

• Silicon Lab Inc

Inventors

• Marques Tiago

Classifications

• H03B2200/004

  including a variable capacitance, e.g. a varicap, a varactor or a variable capacitance of a diode or transistor · CPC title

• H03B2200/0062

  Bias and operating point · CPC title

• H03B5/366 Primary

  and comprising means for varying the frequency by a variable voltage or current · CPC title

• H03B2200/005

  including measures to switch a capacitor · CPC title

• H03B2200/0066

  Amplitude or AM detection · CPC title