Semiconductor device

Patent metadata

Field	Value
Publication number	US-10453957-B2
Application number	US-201715449329-A
Country	US
Kind code	B2
Filing date	Mar 3, 2017
Priority date	Sep 16, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A semiconductor device includes a first semiconductor region, a second semiconductor region between a first gate electrode and a second gate electrode that is disposed apart from the first gate electrode in a first direction, third and fourth semiconductor regions provided on respective portions of the second semiconductor region, an insulating region provided between the third semiconductor region and the fourth semiconductor region, and an electrode provided on the third semiconductor region and the fourth semiconductor region and electrically connected to the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region is parallel to the third semiconductor region in a direction intersecting the first direction. The fourth semiconductor region has an impurity concentration higher than that of the second semiconductor region. A lower end of the insulating region is positioned lower than a boundary surface of the second semiconductor region and the third semiconductor region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor region of a first conductivity type having a first surface;
a first gate insulating region;
a first gate electrode provided on the first semiconductor region via the first gate insulating region;
a second gate insulating region;
a second gate electrode provided on the first semiconductor region via the second gate insulating region, the second gate electrode being disposed apart from the first gate electrode in a first direction;
a second semiconductor region of a second conductivity type provided on the first semiconductor region on a second surface opposite to the first surface and between the first gate electrode and the second gate electrode;
at least one third semiconductor region of the first conductivity type provided on a portion of the second semiconductor region;
a fourth semiconductor region of the second conductivity type provided on another portion of the second semiconductor region, the fourth semiconductor region having an impurity concentration of the second conductivity type higher than an impurity concentration of the second semiconductor region;
a metal region provided on the fourth semiconductor region;
at least one insulating region provided between the at least one third semiconductor region and the metal region;
a first electrode provided on the at least one third semiconductor region, the metal region and the at least one insulating region, the first electrode being electrically connected to the at least one third semiconductor region, the metal region and the at least one insulating region; and
a second electrode provided on the first surface,
wherein a top surface of the at least one insulating region, a top surface of the at least one third semiconductor region and a top surface of the metal region are coplanar with each other.

2. The semiconductor device according to claim 1 ,
wherein the at least one insulating region is provided annularly around the metal region;
the metal region and the at least one insulating region are surrounded by the at least one third semiconductor region.

3. The semiconductor device according to claim 1 , wherein the at least one third semiconductor region is formed in plurality and provided between the first gate electrode and the second gate electrode;
the at least one insulating region is formed in plurality and provided between the first gate electrode and the second gate electrode;
the plurality of insulating regions are provided between the plurality of third semiconductor regions in the first direction;
the metal region is provided between the plurality of insulating regions in the first direction.

4. The semiconductor device according to claim 1 , wherein the at least one third semiconductor region, the metal region and the at least one insulating region are parallel with each other in a second direction intersecting the first direction;
the metal region and the at least one insulating region are in contact with the first gate electrode and the second gate electrode.

Assignees

• Toshiba Kk

Inventors

• Kobayashi Kenya
• Maeyama Kenji
• Matsuo Koji
• Kawaguchi Yusuke

Classifications

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title