Display device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10453871-B2
Application number	US-201815871075-A
Country	US
Kind code	B2
Filing date	Jan 15, 2018
Priority date	Aug 1, 2014
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A display device including a substrate including a display area and a non-display area, a common electrode line in the non-display area, and a protective layer coating at least a part of an end portion of the common electrode line.

First claim

What is claimed is:

1. A method for manufacturing a display device, the method comprising:
forming a display area and a non-display area on a substrate, wherein the non-display area surrounds the display area;
forming a common electrode line in the non-display area on the substrate, the common electrode line having a width measured in a direction extending from the display area to the non-display area with a first end and an opposite second end; and
forming a protective layer covering the first end of the common electrode line and spaced apart from the second end of the common electrode line when viewed in a planar view,
wherein a common electrode coupling portion is coupled to the common electrode line, and
wherein the common electrode coupling portion is spaced apart from the protective layer.

2. The method of claim 1 , wherein the forming of the display area comprises forming a thin film transistor on the substrate, and the forming of the thin film transistor comprises:
forming a semiconductive layer;
forming a gate electrode overlapping the semiconductive layer at least in part;
forming a source electrode coupled to the semiconductive layer; and
forming a drain electrode separated from the source electrode and coupled to the semiconductive layer,
wherein the forming of the source and drain electrodes is performed utilizing substantially the same process as the forming of the common electrode line.

3. The method of claim 2 , further comprising forming a planarization layer on the thin film transistor after the forming of the thin film transistor,
wherein the forming of the planarization layer is performed utilizing substantially the same process as the forming of the protective layer.

4. The method of claim 3 , wherein the forming of the planarization layer comprises:
forming a material layer for the planarization layer by applying a planarization layer-forming material on the thin film transistor;
selectively exposing the material layer for the planarization layer to light; and
developing the exposed material layer for the planarization layer.

5. The method of claim 1 , wherein the forming of the display area comprises forming one or more display elements,
wherein the forming of the display element comprises:
forming a pixel electrode on the substrate;
forming a light emission layer on the pixel electrode; and
forming a common electrode on the light emission layer,
wherein the common electrode is coupled to the common electrode line.

6. The method of claim 5 , further comprising forming a pixel defining layer on the substrate after the forming of the pixel electrode and before the forming of the light emission layer.

7. The method of claim 1 , wherein the forming of the protective layer comprises forming a first protective layer and a second protective layer separated from each other.

8. The method of claim 7 , wherein a distance between the first and the second protective layers is in a range of about 20 μm to about 2000 μm.

9. The method of claim 7 , wherein the forming of the protective layer comprises forming a first protective layer covering at least a part of the first end of the common electrode line, and forming a second protective layer not covering the first end of the common electrode line, the first and second protective layers being alternately arranged.

10. The method of claim 1 , wherein the protective layer has a width in a range of about 20 μm to about 200 μm.

11. The method of claim 1 , wherein the second end of the common electrode line is between the display area and the first end of the common electrode line when viewed in a planar view.

12. The method of claim 1 , wherein the common electrode coupling portion directly contacts the common electrode line.

13. The method of claim 1 , wherein the forming of the protective layer comprises forming a plurality of protective layers spaced apart from each other when viewed in a planar view, and wherein each of the plurality of protective layers covers the first end of the common electrode line and is spaced apart from the second end of the common electrode line when viewed in a planar view.

14. The method of claim 13 , wherein the plurality of protective layers are spaced apart from each other in a direction substantially perpendicular to the width direction of the common electrode line when viewed in a planar view.

Assignees

• Samsung Display Co Ltd

Inventors

• Kwon So Ra
• Go Jae Kyung

Classifications

• H01L27/124

  Electricity · mapped topic

• H01L27/2418

  Electricity · mapped topic

• H01L27/1248 Primary

  Electricity · mapped topic

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10B63/22

  of the metal-insulator-metal type · CPC title