Semiconductor devices and semiconductor packages including magnetic shielding layers and methods of manufacturing semiconductor devices and semiconductor packages

Patent metadata

Field	Value
Publication number	US-10453801-B2
Application number	US-201615093006-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Aug 13, 2015
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

First claim

What is claimed is:

1. A method of manufacturing a magnetic random-access memory (MRAM) device, the method comprising:
forming a plurality of semiconductor chips on a wafer, each of the plurality of semiconductor chips including a MRAM having a perpendicular magnetic tunnel junction (pMTJ) structure;
forming at least one hole through each of the plurality of semiconductor chips;
depositing a ferromagnetic material on the wafer to form a via shielding layer and an upper shielding layer, the via shielding layer filling the at least one hole through each of the plurality of semiconductor chips, the upper shielding layer covering a top surface of each of the plurality of semiconductor chips, and the upper shielding layer connected to the via shielding layer;
patterning the upper shielding layer to expose portions of each of the semiconductor chips, the portions of each of the semiconductor chips including scribe lanes, and pads of a corresponding semiconductor chip among the plurality of semiconductor chips, and removing the upper shielding layer from each outer boundary of each of the semiconductor chips which goes beyond the scribe lanes, the via shielding layer extends along at most two outer edges of the shielding layer; and
sawing the wafer along the scribe lanes to singulate each of the plurality of semiconductor chips.

2. A method of manufacturing a magnetic random-access memory (MRAM) package, the method comprising:
preparing a MRAM device, the MRAM device including
a semiconductor chip including a MRAM, the MRAM having a perpendicular magnetic tunnel junction (pMTJ) structure, and
a magnetic shielding layer including an upper shielding layer and a via shielding layer, the upper shielding layer on a top surface of the semiconductor chip, and the via shielding layer extending from the upper shielding layer through the semiconductor chip;

depositing a ferromagnetic material on a package substrate to form a substrate shielding layer;
stacking the MRAM device on the package substrate to connect the via shielding layer to the substrate shielding layer; and
forming a sealing material to seal the MRAM device;
wherein the preparing of the MRAM device includes
forming a plurality of semiconductor chips on a wafer, each of the plurality of semiconductor chips including a MRAM having a pMTJ structure,
forming at least one hole through each of the plurality of semiconductor chips;
depositing a ferromagnetic material on the wafer to form a via shielding layer and an upper shielding layer, the via shielding layer filling the at least one hole formed through each of the plurality of semiconductor chips, and the upper shielding layer covering a top surface of each of the plurality of semiconductor chips, the upper shielding layer connected to the via shielding layer;
patterning the upper shielding layer to remove portions of the upper shielding layer at portions of each of the semiconductor chips, the portions of each of the semiconductor chips including scribe lanes and pads of a corresponding semiconductor chip among the plurality of semiconductor chips, and removing the upper shielding layer from each outer boundary of each of the plurality of semiconductor chips which goes beyond the scribe lanes, the via shielding layer extends along at most two outer edges of the shielding laver; and
sawing the wafer along the scribe lanes to singulate each of the plurality of semiconductor chips.

3. A method of manufacturing a magnetic random access memory (MRAM) device, the method comprising:
forming at least one first through-hole through a semiconductor wafer;
forming a ferromagnetic layer on the semiconductor wafer, the ferromagnetic layer filling the at least one first through-hole;
patterning the ferromagnetic layer to expose a scribe lane and at least a first pad area portion on an upper surface of the semiconductor wafer, and to form a magnetic shielding layer, the magnetic shielding layer including at least a via shielding layer filling the at least one first through-hole, and removing the ferromagnetic layer from each outer boundary of the semiconductor wafer which goes beyond the scribe lanes, a plurality of the at least one first through-holes extends along only one outer edges of the magnetic shielding layer; and
cutting the semiconductor wafer along the scribe lane to form the MRAM device.

4. The method of claim 3 , wherein the at least one first through-hole has an elongated edge that is parallel to an edge of the MRAM device.

5. The method of claim 3 , further comprising:
forming at least one second through-hole through the semiconductor wafer, the at least one first through-hole and the at least one second through-hole spaced apart from one another in a plane of the upper surface of the semiconductor wafer; and
wherein the patterning includes
removing at least a first portion of the ferromagnetic layer to expose the first pad area portion and the scribe lane on the upper surface of the semiconductor wafer, and to form an upper shielding layer on the upper surface of the semiconductor wafer, wherein
the via shielding layer fills the at least one first through-hole and the at least one second through-hole.

6. The method of claim 5 , wherein a bottom surface of the via shielding layer is planar with a bottom surface of the semiconductor wafer.

7. The method of claim 5 , wherein a bottom surface of the via shielding layer protrudes from a bottom surface of the semiconductor wafer.

8. The method of claim 5 , wherein the first pad area portion is between the at least one first through-hole and the at least one second through-hole.

9. The method of claim 8 , wherein a bottom surface of the via shielding layer protrudes from a bottom surface of the semiconductor wafer.

10. The method of claim 5 , wherein the patterning comprises:
removing at least a second portion of the ferromagnetic layer to expose a second pad area portion on the upper surface of the semiconductor wafer; wherein
the first pad area portion is at a first side of the upper surface of the semiconductor wafer,
the second pad area portion is at a second side of the upper surface of the semiconductor wafer, and
the first and second sides are opposite one another.

11. The method of claim 5 , wherein
the first pad area portion is at a first side of the upper surface of the semiconductor wafer;
the first through-hole and the second through-hole are at a second side of the semiconductor wafer; and
the first side is opposite to the second side.

12. The method of claim 5 , wherein
the forming at least one first through-hole includes
forming a pair of first through-holes along opposite edges of the semiconductor wafer; and
the forming at least one second through-hole includes forming a pair of second through-holes along opposite edges of the semiconductor wafer;

the first pad area portion is between the pair of first through-holes and the pair of second through-holes; and
the via shielding layer fills the pair of first through-holes and the pair of second through-holes.

13. The method of claim 5 , wherein the first pad area portion is exposed through a central portion of the ferromagnetic layer.

14. The method of claim 5 , wherein
the forming at least one first through-hole includes
forming a plurality of first through-holes along a first edge of the semiconductor wafer;

the forming at least one second through-hole includes
forming a plurality of second through-holes along a second edge of the semiconductor wafer, the second edge being opposite to the first edge; and

the via shielding layer fills the plurality of first through-ho

Assignees

• Seo Bo Young
• Lee Yong Kyu
• Samsung Electronics Co Ltd

Inventors

• Seo Bo-Young
• Lee Yong-Kyu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title