Interconnection structures and fabrication methods thereof

US10453797B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10453797-B2
Application numberUS-201715821581-A
CountryUS
Kind codeB2
Filing dateNov 22, 2017
Priority dateNov 29, 2016
Publication dateOct 22, 2019
Grant dateOct 22, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive structure in the dielectric layer, forming a cap layer doped with silicon on the conductive structure and the dielectric layer, and performing an annealing process on the conductive structure and the cap layer. During the annealing process, the silicon ions in the cap layer react with the material of the conductive structure and form chemical bonds. As such, the connection strength between the cap layer and the conductive structure is improved, which is conducive to suppressing electro migration in the formed interconnection structure. Therefore, the reliability of the formed interconnection structure is improved.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for fabricating an interconnection structure, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a conductive structure in the dielectric layer; forming a cap layer doped with silicon on the conductive structure and the dielectric layer, wherein the cap layer has a bi-layer structure; and performing an annealing process on the conductive structure and the cap layer, wherein along a direction away from the conductive structure, a doping concentration of silicon in the cap layer gradually decreases. 2. The method for fabricating the interconnection structure according to claim 1 , wherein: the cap layer is made of a material including silicon-doped AlN. 3. The method for fabricating the interconnection structure according to claim 1 , wherein: the cap layer is formed by an atomic layer deposition. 4. The method for fabricating the interconnection structure according to claim 3 , wherein forming the cap layer further includes: forming an AlSiN layer on the conductive structure and the dielectric layer; and forming an AlN layer on the AlSiN layer. 5. The method for fabricating the interconnection structure according to claim 4 , wherein: a ratio between a thickness of the AlSiN layer and a thickness of the AlN layer is in a range of 3:1 to 2:1. 6. The method for fabricating the interconnection structure according to claim 1 , wherein: an atomic percentage of the silicon doped in the cap layer is in a range of approximately 10% to approximately 20%. 7. The method for fabricating the interconnection structure according to claim 1 , after forming the conductive structure and prior to forming the cap layer, further including: performing a plasma pre-treatment process on a surface of the dielectric layer. 8. The method for fabricating the interconnection structure according to claim 1 , wherein performing the plasma pre-treatment process includes: using plasma of trisilylamine to treat the surface of the dielectric layer. 9. The method for fabricating the interconnection structure according to claim 1 , wherein: the dielectric layer is made of an ultra-low-k dielectric material with a dielectric constant lower than 2.5; and the conductive structure is made of Cu. 10. A method for fabricating an interconnection structure, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a conductive structure in the dielectric layer; forming a cap layer doped with silicon on the conductive structure and the dielectric layer; controlling a doping concentration of the silicon in the cap layer to gradually decrease along a direction away from the conductive structure; and performing an annealing process on the conductive structure and the cap. 11. The method for fabricating the interconnection structure according to claim 10 , wherein: forming the cap layer further includes at least one time of deposition of a silicon-doped material; each time of the deposition of the silicon-doped material includes absorbing an Al-containing atomic layer, absorbing a Si-containing atomic layer on the Al-containing atomic layer, and performing a nitrogen treatment process on the Al-containing atomic layer and the Si-containing atomic layer; and absorbing the Si-containing atomic layer on the Al-containing atomic layer includes introducing a Si-containing reaction gas including SiH 4 , and removing remaining Si-containing reaction gas by purging. 12. The method for fabricating the interconnection structure according to claim 11 , wherein: deposition of the silicon-doped material is performed multiple times; and a flow rate of SiH 4 gradually decreases during the multiple times of deposition of the silicon-doped material. 13. The method for fabricating the interconnection structure according to claim 11 , wherein: deposition of the silicon-doped material is performed for multiple times; and a process time to introduce SiH 4 gradually decreases during the multiple times of the deposition of the silicon-doped material. 14. An interconnection structure, comprising: a substrate; a dielectric layer formed on the substrate; a conductive structure formed in the dielectric layer; and a cap layer doped with silicon and formed on the conductive structure and the dielectric layer, wherein along a direction away from the conductive structure, a doping concentration of silicon in the cap layer gradually decreases. 15. The interconnection structure according to claim 14 , wherein: the cap layer is made of a material including silicon-doped AlN. 16. The interconnection structure according to claim 14 , wherein: an atomic percentage of the silicon doped in the cap layer is in a range of approximately 10% to approximately 20%. 17. The interconnection structure according to claim 14 , wherein the cap layer has a bi-layer structure including: an AlSiN layer; and an AlN layer formed on the AlSiN layer. 18. The interconnection structure according to claim 17 , wherein: a ratio between a thickness of the AlSiN layer and a thickness of the AlN layer is in a range of 3:1 to 2:1. 19. The interconnection structure according to claim 14 , wherein: the dielectric layer is made of an ultra-low-k dielectric material with a dielectric constant lower than 2.5; and the conductive structure is made of Cu.

Assignees

Inventors

Classifications

  • the material containing aluminium, e.g. Al2O3 · CPC title

  • the material containing aluminium, e.g. AlSiOx · CPC title

  • the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

  • by exposure to a plasma · CPC title

  • deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

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What does patent US10453797B2 cover?
A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive structure in the dielectric layer, forming a cap layer doped with silicon on the conductive structure and the dielectric layer, and performing an annealing process on the conductive structure and the cap layer. During the annealing process, the …
Who is the assignee on this patent?
Semiconductor Mfg Int Shanghai Corp, Semiconductor Mfg Int Beijing Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/056. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 22 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).