Apparatus and methods including establishing a negative body potential in a memory cell

Patent metadata

Field	Value
Publication number	US-10453538-B2
Application number	US-201816035933-A
Country	US
Kind code	B2
Filing date	Jul 16, 2018
Priority date	Nov 14, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.

First claim

What is claimed is:

1. A method of operating an apparatus, comprising:
advancing a timer; and
establishing a negative potential in a body of a memory cell of a memory in response to a value of the timer having a desired value.

2. The method of claim 1 , wherein the timer is external to the memory, and wherein establishing the negative potential in the body of the memory cell is performed in response to a command received by the memory from a device external to the memory that is in communication with the timer.

3. The method of claim 1 , wherein the timer comprises a counter responsive to a clock signal, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to a count value of the counter having the desired value.

4. The method of claim 3 , further comprising:
resetting the counter to an initial value after the count value has the desired value.

5. The method of claim 3 , further comprising:
modifying the desired value of the count value in response to a temperature sensor indicating a temperature higher than a predefined upper threshold or lower than a predefined lower threshold.

6. The method of claim 1 , wherein the timer is configured to periodically toggle a logic level of an output signal from a first logic level to a second logic level at intervals of some particular elapsed time, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to the output signal having the second logic level.

7. The method of claim 6 , further comprising:
increasing a length of the intervals in response to a temperature sensor indicating a temperature higher than a predefined upper threshold; and
decreasing a length of the intervals in response to a temperature sensor indicating a temperature lower than a predefined lower threshold.

8. The method of claim 1 , wherein establishing the negative potential in the body of the memory cell comprises applying a negative voltage level to a source connected to the body of the memory cell.

9. The method of claim 1 , wherein the memory cell is a particular memory cell of a string of series-connected memory cells, and wherein establishing the negative potential in the body of the memory cell comprises applying a same positive voltage level to each access line of a plurality of access lines, where each access line of the plurality of access lines is connected to a respective memory cell of the string of series-connected memory cells.

10. The method of claim 1 , further comprising initiating a sensing operation on the memory cell while the body of the memory cell has the negative potential.

11. The method of claim 1 , wherein the timer is configured to toggle a logic level of an output signal at intervals of some particular elapsed time, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to the output signal having a particular logic level.

12. The method of claim 11 , further comprising:
modifying a length of the intervals in response to an indication of temperature.

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji
• Hawes Mark
• Tanzawa Toru
• Binfet Jeremy

Classifications

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title