NAND flash memory device performing continuous reading operation using NOR compatible command, address and control scheme

Patent metadata

Field	Value
Publication number	US-10453524-B2
Application number	US-201715614631-A
Country	US
Kind code	B2
Filing date	Jun 6, 2017
Priority date	Sep 27, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory of the invention includes a memory cell array; a page reading element, which selects a page of the memory cell array and reads out data of the selected page to a page buffer/sense circuit; a page information storage element, which stores page information related to a range of a continuous reading; and a control element, which controls the continuous reading of the page. The control element determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
an input/output buffer, receiving an external control signal;
a memory cell array;
a word line select circuit, for selecting a page of the memory cell array and reading out data of the selected page to a page buffer; and
a controller, for setting page information related to a range of a continuous reading of the page and controlling the continuous reading of the page of the word line select circuit,
wherein the controller determines whether to resume a continuous reading mode based on the page information,
wherein if determining to resume the continuous reading mode, the controller stores a page address and a column address when the external control signal is disabled and continues to hold the data read out by the word line select circuit, and the controller outputs the data read out by the word line select circuit based on the stored page address and the column address when the external control signal is enabled.

2. The semiconductor memory device according to claim 1 , wherein
the controller determines to resume the continuous reading mode when the page selected by the word line select circuit is within a page range defined by the page information, and the controller determines not to resume the continuous reading mode when the selected page is outside the page range.

3. The semiconductor memory device according to claim 1 , wherein
if determining not to resume the continuous reading mode, the controller ends the continuous reading in response to the external control signal being disabled, and if determining to resume the continuous reading mode, the controller is capable of performing the continuous reading without a page data read command being inputted when the external control signal being disabled is immediately enabled.

4. The semiconductor memory device according to claim 1 , wherein
the controller performing an operation of storing the page information in a page information storage part.

5. The semiconductor memory device according to claim 1 , wherein
the controller sets at least one pair of a minimum page address and a maximum page address as the page information.

6. The semiconductor memory device according to claim 1 , wherein
the controller sets a burst length for defining a number of pages used in the continuous reading as the page information.

7. The semiconductor memory device according to claim 1 , wherein
a page firstly selected by the word line select circuit during the continuous reading is designated based on the page address being inputted.

8. The semiconductor memory device according to claim 1 , wherein
a page firstly selected by the word line select circuit during the continuous reading is designated based on a predetermined page address.

9. The semiconductor memory device according to claim 8 , wherein
the predetermined page address is a page address firstly read out from the memory cell array when a power is on.

10. The semiconductor memory device according to claim 1 , wherein
the semiconductor memory device further comprises:
an output buffer, for serially outputting data of the continuous reading in response to an external serial clock.

11. The semiconductor memory device according to claim 10 , wherein
the output buffer comprises a data register, the data register holding data forwarded from the page buffer, the data of the selected page of the memory cell array being held in the page buffer during a period when data is outputted from the data register.

12. The semiconductor memory device according to claim 1 , wherein
the semiconductor memory device is an NAND flash memory.

13. A flash memory, comprising:
an input/output buffer, receiving an external control signal;
an NAND memory cell array;
a page buffer, for holding data forwarded from a selected page of the memory cell array or holding to-be-programmed data;
a data register, capable of performing a bidirectional data transceiving with the page buffer; and
a controller, for continuously reading out a page of the memory cell array and serially outputting read data through the data register in synchronism with a serial clock and setting page information related to a range of a continuous reading,
wherein the controller being capable of performing the continuous reading within a page range defined by the page information without a page data read command,
wherein if determining to resume a continuous reading mode, the controller stores a page address and a column address when the external control signal is disabled and continues to hold data read out by a word line select circuit, and the controller outputs the data read out by the word line select circuit based on the stored page address and the column address when the external control signal is enabled.

14. The flash memory according to claim 13 , wherein
the flash memory is set active in response to a logic level of an external control signal, and the controller still resumes a continuous reading mode even if the external control signal is toggled.

15. A continuous reading method of a flash memory, comprising:
receiving, by an input/output buffer, an external control signal;
setting page information related to a range of a continuous reading;
performing the continuous reading without a page data read command even if the external control signal is disabled when the continuous reading is performed within the range defined by the page information; and
if determining to resume a continuous reading mode, storing a page address and a column address when the external control signal is disabled and continues to hold data read out by a word line select circuit, and outputting the data read out by the word line select circuit based on the stored page address and the column address when the external control signal is enabled.

16. The continuous reading method according to claim 15 , wherein
the continuous reading method further comprises:
serially outputting page data in synchronism with a serial clock.

17. A semiconductor memory device, comprising:
a memory cell array;
a word line select circuit, for selecting a page of the memory cell array and reading out data of the selected page to a page buffer; and
a controller, for setting page information related to a range of a continuous reading of the page and controlling the continuous reading of the page of the word line select circuit,
wherein the controller determines a continuous reading mode is resumed based on the page information,
wherein a page firstly selected by the word line select circuit during the continuous reading is designated based on a predetermined page address,
the predetermined page address is a page address firstly read out from the memory cell array when a power is on.

18. The semiconductor memory device according to claim 17 , wherein
the controller sets at least one pair of a minimum page address and a maximum page address as the page information.

19. The semiconductor memory device according to claim 17 , wherein
the controller sets a burst length for defining a number of pages used in the continuous reading as the page information.

Assignees

• Winbond Electronics Corp

Inventors

• Kaminaga Takehiro
• Suito Katsutoshi

Classifications

• G11C29/46

  Test trigger logic · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title