Memory module voltage regulator module (VRM)

Patent metadata

Field	Value
Publication number	US-10453516-B2
Application number	US-201815899514-A
Country	US
Kind code	B2
Filing date	Feb 20, 2018
Priority date	Feb 27, 2015
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

First claim

What is claimed is:

1. A memory module comprising:
a voltage regulator module (VRM) to receive input power, and provide output power to components of the memory module on a first power plane;
an electrical gap to electrically isolate the first power plane from a second power plane associated with at least one contact of the memory module; and
at least one stitching capacitor to couple the first power plane to the at least one contact associated with the second power plane.

2. The memory module of claim 1 , wherein the memory module is backward compatible with a motherboard that is capable of providing, to memory modules, the input power and the output power based on a multi-phase voltage regulator, wherein the gap is to isolate the memory module output power from that of the motherboard, and the memory module is based on a backward compatible form factor to interface with the motherboard.

3. The memory module of claim 1 , wherein the at least one contact comprises at least one finger pin contact to interface with a motherboard.

4. The memory module of claim 3 , wherein the VRM is to identify a reference value for setting the output voltage, based on substantially matching a motherboard output voltage within acceptable design tolerances.

5. The memory module of claim 1 , wherein signals allowed to pass by the at least one stitching capacitor include return current of memory address and command signals.

6. The memory module of claim 1 , wherein the VRM is integrated with a serial presence detect (SPD) chip of the memory module.

7. The memory module of claim 1 , wherein the VRM is integrated with a register chip of the memory module.

8. The memory module of claim 1 , wherein the memory module is a double data rate, type four, synchronous dynamic random-access memory (DDR4 SDRAM) dual inline memory module (DIMM), including a power distribution network (PDN) contained on the memory module to distribute power from the VRM to the components of the memory module.

9. The memory module of claim 1 , wherein the at least one stitching capacitor is appropriate to provide an AC signal return path without signal integrity degradation.

10. A system comprising:
a memory module including a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane; and
a motherboard including a single-phase voltage regulator to provide the input power to the memory module via a motherboard memory slot coupled to a motherboard power pad for power delivery by a second power plane, wherein the motherboard power pad has an appropriate size to accommodate the power associated with the components of the motherboard;
wherein the memory module includes at least one stitching capacitor to couple the first power plane, associated with the VRM output, to the second power plane associated with the motherboard.

11. The system of claim 10 , wherein the motherboard is to receive AC return current of command address signals from components of the memory module via at least one stitching capacitor of the memory module.

12. The system of claim 10 , wherein the single-phase voltage regulator is to supply 10 Amp power to the VRM of the memory module, and the power pad is sized to accommodate the 10 Amp output of the single-phase voltage regulator.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Bacchus Reza M
• Benedict Melvin K
• Contreras Stephen F
• Pope Eric L
• Sides Chi K
• Huang Chun-Pin

Classifications

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title