Circuit arrangement, method of forming and operating the same

Patent metadata

Field	Value
Publication number	US-10453511-B2
Application number	US-201716079511-A
Country	US
Kind code	B2
Filing date	Feb 16, 2017
Priority date	Feb 25, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Various embodiments may provide a circuit arrangement. The circuit arrangement may include a first spin-orbit torque magnetic tunnel junction cell, a second spin-orbit torque magnetic tunnel junction cell, a first driver circuit arrangement, a second driver circuit arrangement, and a read circuit arrangement. The circuit arrangement allows for the operation of a non-volatile flip-flop based on spin-orbit torque effect.

First claim

The invention claimed is:

1. A circuit arrangement comprising:
a first spin-orbit torque magnetic tunnel junction cell having a reference terminal, a first electrode terminal, and a second electrode terminal;
a second spin-orbit torque magnetic tunnel junction cell having a reference terminal, a first electrode terminal, and a second electrode terminal;
a first driver circuit arrangement connected to the second electrode terminal of the first spin-orbit torque magnetic tunnel junction cell and the first electrode terminal of the second spin-orbit torque magnetic tunnel junction cell;
a second driver circuit arrangement connected to the first electrode terminal of the first spin-orbit torque magnetic tunnel junction cell and the second electrode terminal of the second spin-orbit torque magnetic tunnel junction cell;
a read circuit arrangement connected to the reference terminal of the first spin-orbit torque magnetic tunnel junction cell and the reference terminal of the second spin-orbit torque magnetic tunnel junction cell;
wherein the first driver circuit arrangement and the second driver circuit arrangement are configured so that a first write current flowing from the first driver circuit arrangement to the second driver circuit arrangement generates a first logic state in the first spin-orbit torque magnetic tunnel junction cell and a second logic state in the second spin-orbit torque magnetic tunnel junction cell, and a second write current flowing from the second driver circuit arrangement to the first driver circuit arrangement generates the second logic state in the first spin-orbit torque magnetic tunnel junction cell and the first logic state in the second spin-orbit torque magnetic tunnel junction cell; and
wherein the read circuit arrangement is configured to flow a first sense current through the first spin-orbit torque magnetic tunnel junction cell and a second sense current through the second spin-orbit torque magnetic tunnel junction cell for determining a logic state of the first spin-orbit torque magnetic tunnel junction cell and a logic state of the second spin-orbit torque magnetic tunnel junction cell.

2. The circuit arrangement according to claim 1 ,
wherein the first spin-orbit torque magnetic tunnel junction cell comprises:
a magnetic tunneling junction; and
an electrode in contact with the magnetic tunneling junction; and

wherein the second spin-orbit torque magnetic tunnel junction cell comprises:
a magnetic tunneling junction; and
an electrode in contact with the magnetic tunneling junction.

3. The circuit arrangement according to claim 1 ,
wherein the first electrode terminal of the first spin-orbit torque magnetic tunnel junction cell is at a first end of the electrode of the first spin-orbit torque magnetic tunnel junction cell;
wherein the second electrode terminal of the first spin-orbit torque magnetic tunnel junction cell is at a second end of the electrode of the first spin-orbit torque magnetic tunnel junction cell;
wherein the first electrode terminal of the second spin-orbit torque magnetic tunnel junction cell is at a first end of the electrode of the second spin-orbit torque magnetic tunnel junction cell; and
wherein the second electrode terminal of the second spin-orbit torque magnetic tunnel junction cell is at a second end of the electrode of the second spin-orbit torque magnetic tunnel junction cell.

4. The circuit arrangement according to claim 2 ,
wherein the magnetic tunneling junction of the first spin-orbit torque magnetic tunnel junction cell comprises:
a reference layer having a fixed magnetization;
a storage layer configured to switch between a first magnetization state and a second magnetization state; and
a tunneling barrier separating the reference layer and the storage layer.

5. The circuit arrangement according to claim 4 ,
wherein the reference terminal of the first spin-orbit torque magnetic tunnel junction cell is at the reference layer of the magnetic tunneling junction of the first spin-orbit torque magnetic tunnel junction cell.

6. The circuit arrangement according to claim 4 ,
wherein the first spin-orbit torque magnetic tunnel junction cell is configured so that the first logic state of the first spin-orbit torque magnetic tunnel junction cell is generated when the storage layer of the first spin-orbit torque magnetic tunnel junction cell is at the first magnetization state; and
wherein the first spin-orbit torque magnetic tunnel junction cell is configured so that the second logic state of the first spin-orbit torque magnetic tunnel junction cell is generated when the storage layer of the first spin-orbit torque magnetic tunnel junction cell is at the second magnetization state.

7. The circuit arrangement according to claim 2 ,
wherein the second magnetic tunneling junction of the second spin-orbit torque magnetic tunnel junction cell comprises:
a reference layer having a fixed magnetization;
a storage layer configured to switch between a first magnetization state and a second magnetization state; and
a tunneling barrier separating the reference layer and the storage layer.

8. The circuit arrangement according to claim 7 ,
wherein the reference terminal of the second spin-orbit torque magnetic tunnel junction cell is at the reference layer of the magnetic tunneling junction of the first spin-orbit torque magnetic tunnel junction cell.

9. The circuit arrangement according to claim 7 ,
wherein the second spin-orbit torque magnetic tunnel junction cell is configured so that the first logic state of the second spin-orbit torque magnetic tunnel junction cell is generated when the storage layer of the second spin-orbit torque magnetic tunnel junction cell is at the first magnetization state; and
wherein the second spin-orbit torque magnetic tunnel junction cell is configured so that the second logic state of the second spin-orbit torque magnetic tunnel junction cell is generated when the storage layer of the second spin-orbit torque magnetic tunnel junction cell is at the second magnetization state.

10. The circuit arrangement according to claim 1 ,
wherein the read circuit arrangement comprises a differential sense amplifier, the differential sense amplifier comprising:
a first input connected to the reference terminal of the first spin-orbit torque magnetic tunnel junction cell; and
a second input connected to the reference terminal of the second spin-orbit torque magnetic tunnel junction cell.

11. The circuit arrangement according to claim 10 ,
wherein the differential sense amplifier is configured to generate an output based on the determination of the logic state of the first spin-orbit torque magnetic tunnel junction cell and the logic state of the second spin-orbit torque magnetic tunnel junction cell.

12. The circuit arrangement according to claim 1 ,
wherein the first driver circuit arrangement is configured to receive a clock signal and a first input voltage; and
wherein the second driver circuit arrangement is configured to receive the clock signal and a second input voltage.

13. The circuit arrangement according to claim 12 ,
wherein the first driver circuit arrangement is configured to generate a first voltage based on the clock signal, and the first input voltage; and
wherein the second driver circuit arrangement is configured to generate a second voltage based on the clock signal, and the second input voltage.

14. The circuit arrangement according to claim 13 ,
wherein the first write current flows from the first driver circuit arrangement to the second driver circuit arrangement when the first vol

Assignees

• Agency Science Tech & Res

Inventors

• Lua Sunny Yan Hwee
• Mani Aarthy

Classifications

• G11C11/1697

  Power supply circuits · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title