Phase locked loop (PLL)

Patent metadata

Field	Value
Publication number	US-10447282-B2
Application number	US-201815863672-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Jul 20, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A phase locked loop (PLL) includes a first charge pump coupled to a filter. The first charge pump may feed the filter a first current. A second charge pump is coupled to the filter. The second charge pump may feed the filter a second current. A first gate is coupled to an input of the second charge pump. The first gate selectively gates the second current.

First claim

What is claimed is:

1. A phase locked loop (PLL) comprising:
a first charge pump coupled to a filter having first and second input nodes, the first charge pump coupled to the first input node, the first charge pump configured to feed the filter a first current via the first input node;
a second charge pump coupled to the filter via the second input node, the second charge pump configured to feed the filter a second current via the second input node; and
a first gate coupled to the second charge pump, the first gate configured to selectively provide an input signal to the second charge pump, in which only the second charge pump of the first and the second charge pumps is gated at its input so that the second current is injected less often, in which a phase detector is coupled to the first charge pump to provide an input signal to the first charge pump.

2. The PLL of claim 1 , further comprising:
a third charge pump coupled to the filter, the third charge pump configured to feed the filter a third current; and
a second gate coupled to the third charge pump, the second gate configured to selectively gate the third current.

3. The PLL of claim 2 , further comprising a phase generator coupled to the first gate, the second gate, and the filter.

4. The PLL of claim 3 , in which the phase generator is configured to generate a phase signal for controlling the first gate and the second gate.

5. The PLL of claim 2 , in which the first gate and the second gate are configured to alternatingly gate a control signal.

6. The PLL of claim 5 , in which the control signal is input to both the first gate and the second gate.

7. The PLL of claim 1 , further comprising a phase generator coupled to the first gate and the filter.

8. The PLL of claim 7 , in which the phase generator is configured to generate a phase signal for controlling the first gate.

9. The PLL of claim 1 , in which the filter comprises an integral capacitor coupled to an output of the second charge pump, and a zeroing amplifier coupled to an output of the first charge pump.

10. The PLL of claim 1 , in which the filter comprises a resampling switch coupled to an output of the second charge pump.

11. The PLL of claim 1 , in which the filter is a loop filter.

12. The PLL of claim 1 , in which the filter comprises a first capacitor coupled to a first switch and a second capacitor coupled to a second switch.

13. The PLL of claim 12 in which the first switch and the second switch are coupled to a same output of the first charge pump.

14. A method of operating a phase locked loop (PLL), comprising:
generating a first current from a first charge pump, the first charge pump coupled to a first input node of a filter;
feeding the first current to the first input node of the filter;
selectively gating a second current generated by a second charge pump, the second charge pump coupled to a second input node of the filter, in which the filter comprises an integral capacitor coupled to an output of the second charge pump, and a zeroing amplifier coupled to an output of the first charge pump; and
selectively gating a third current generated by a third charge pump.

15. The method of claim 14 , further comprising feeding the second current to the second input node of the filter.

16. The method of claim 14 , further comprising feeding the third current to the filter.

17. A phase locked loop (PLL) comprising:
a first charge pump coupled to a filter having first and second input nodes, the first charge pump coupled to the first input node, the first charge pump configured to feed the filter a first current via the first input node;
a second charge pump coupled to the filter via the second input node, the second charge pump configured to feed the filter a second current via the second input node;
first means for restricting current coupled to the second charge pump, the first current restricting means configured to selectively restrict the second current;
a third charge pump coupled to the filter, the third charge pump configured to feed the filter a third current; and
second means for restricting current coupled to the third charge pump, the second current restricting means configured to selectively restrict the third current, in which the first means for restricting and the second means for restricting comprise means for alternatingly restricting a control signal input to both the first means for restricting and the second means for restricting.

18. The PLL of claim 17 , further comprising means for generating phase, the phase generating means coupled to the first means for restricting, the second means for restricting, and the filter.

19. The PLL of claim 17 , further comprising means for generating phase, the phase generating means coupled to the first current restricting means and the filter.

20. The PLL of claim 17 , in which the filter comprises an integral capacitor coupled to an output of the second charge pump, and a zeroing amplifier coupled to an output of the first charge pump.

21. The PLL of claim 17 , in which the filter comprises a resampling switch coupled to an output of the second charge pump.

22. The PLL of claim 17 , in which the filter is a loop filter.

23. The PLL of claim 17 , in which the filter comprises a first capacitor coupled to a first switch and a second capacitor coupled to a second switch.

24. The PLL of claim 23 in which the first switch and the second switch are coupled to a same output of the first charge pump.

Assignees

• Qualcomm Inc

Inventors

• Abcarius John

Classifications

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H04L27/148

  using filters, including PLL-type filters · CPC title

• H04L27/152

  using controlled oscillators, e.g. PLL arrangements · CPC title

• H03L7/0893

  the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title