Low power energy detector

Patent metadata

Field	Value
Publication number	US-10447266-B2
Application number	US-201715849752-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Apr 24, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A wakeup circuit includes an amplification stage circuit and a filter stage circuit. The amplification stage circuit is configured to, in response to receiving an input signal, generate an amplified digital signal that is proportional to the input signal. The filter stage circuit is configured to, in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period (such as one clock period of a clock signal), generate a wakeup signal as an output signal of the filter stage circuit.

First claim

What is claimed is:

1. A wakeup circuit, comprising:
an amplification stage circuit configured to, in response to receiving an input signal, generate an amplified digital signal that is proportional to the input signal; and
a filter stage circuit coupled to the amplification stage circuit, the filter stage circuit configured to, in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period, generate a wakeup signal as an output signal of the filter stage circuit.

2. The wakeup circuit of claim 1 , wherein the amplification stage circuit includes:
a first inverter biased for operation as a linear amplifier, the first inverter configured to receive the input signal and generate an amplified analog version of the input signal; and
a second inverter coupled to the first inverter, the second inverter configured to receive the amplified analog version of the input signal and generate the amplified digital signal.

3. The wakeup circuit of claim 2 , wherein the amplification stage circuit further includes a coupling capacitor coupled to the first inverter, the coupling capacitor configured to have a capacitance to tune a response of the first inverter to be centered on a frequency of the input signal.

4. The wakeup circuit of claim 2 , wherein the first inverter is configured to have a first switching threshold and the second inverter is configured to have a second switching threshold, the first switching threshold being different than the second switching threshold.

5. The wakeup circuit of claim 4 , wherein the second switching threshold is greater than the first switching threshold.

6. The wakeup circuit of claim 1 , wherein the filter stage circuit includes:
an oscillator configured to generate a clock signal with a clock period corresponding to the pre-defined time period; and
a digital filter to receive the amplified digital signal and the clock signal and generate the wakeup signal.

7. The wakeup circuit of claim 6 , wherein the oscillator is a ring oscillator.

8. The wakeup circuit of claim 6 , wherein the digital filter is a synchronous filter.

9. The wakeup circuit of claim 1 , wherein the wakeup signal is a HIGH signal.

10. The wakeup circuit of claim 9 , wherein the filter stage circuit is further configured, in response to receiving less than the threshold number of toggles of the amplified digital signal within one clock period of a clock signal, to reset the output signal to a LOW signal.

11. The wakeup circuit of claim 1 , wherein the filter stage circuit includes:
an oscillator configured to generate a clock signal with a clock period corresponding to the pre-defined time period, and with a clock signal frequency that is less than a frequency of the amplified digital signal; and
a digital filter to receive the amplified digital signal and the clock signal and generate the wakeup signal.

12. A low power mode circuit system, comprising:
a master circuit configured to generate an input signal; and
a slave circuit including:
a wakeup circuit configured to:
receive the input signal;
in response to receiving the input signal, generate an amplified digital signal that is proportional to the input signal;
in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period, generate a wakeup signal; and
a main circuit configured to, in response to receiving the wakeup signal, power up from a low power mode to a regular operation mode.

13. The low power mode circuit system of claim 12 , wherein the wakeup circuit is configured to generate the amplified digital signal utilizing a first inverter biased for operation as a linear amplifier to generate an amplified analog version of the input signal and a second inverter configured to generate the amplified digital signal based on the amplified analog version of the input signal.

14. The low power mode circuit system of claim 13 , wherein the wakeup circuit is further configured to tune a response of the first inverter to be centered on a frequency of the input signal.

15. The low power mode circuit system of claim 13 , wherein the first inverter is configured to have a first switching threshold and the second inverter is configured to have a second switching threshold, the first switching threshold being less than the second switching threshold.

16. The low power mode circuit system of claim 12 , wherein the wakeup circuit is configured to generate the wakeup signal utilizing a digital filter including clock circuitry to generate a clock signal with a clock period corresponding to the pre-defined time period.

17. The low power mode circuit system of claim 16 , wherein:
the wakeup circuit is further configured, in response to receiving less than the threshold number of toggles of the amplified digital signal within one clock period of the clock signal, to set an output signal of the digital filter to a LOW signal; and
the wakeup signal is a HIGH signal of the output signal.

18. A method for generating a wakeup signal, comprising:
receiving an input signal indicating that a circuit is to exit a low power mode from a master circuit;
in response to receiving the input signal, generating an amplified digital signal that is proportional to the input signal; and
in response to receiving a threshold number of toggles of the amplified digital signal within a pre-defined time period, generating, by a digital filter, the wakeup signal.

19. The method of claim 18 , wherein the generating the amplified digital signal includes:
generating an amplified version of the input signal utilizing a first inverter biased for operation as a linear amplifier; and
generating the amplified digital signal utilizing a second inverter.

20. The method of claim 18 , further comprising, in response to receiving less than the threshold number of toggles of the amplified digital signal within the pre-defined time period, setting an output signal of the digital filter to a LOW signal, wherein the wakeup signal is a HIGH signal of the output signal of the digital filter.

Assignees

• Texas Instruments Inc

Inventors

• Arora Anurag
• Nagarajan Hariharan
• Seth Sumantra

Classifications

• H04L12/12

  Arrangements for remote connection or disconnection of substations or of equipment thereof · CPC title

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H04L12/40006

  Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90) · CPC title

• Y02D30/50

  in wire-line communication networks, e.g. low power modes or reduced link rate · CPC title