High quality factor time delay filters using multi-layer fringe capacitors

Patent metadata

Field	Value
Publication number	US-10447228-B2
Application number	US-201816215539-A
Country	US
Kind code	B2
Filing date	Dec 10, 2018
Priority date	Apr 25, 2016
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.

First claim

We claim:

1. A multilayer fringe capacitor comprising:
a third layer, comprising first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface;
a second layer, below the third layer, the second layer comprising first and second sets of coupling vias and insulative core material, the insulative core material characterized by a first dielectric constant and separating the first and second sets of vias; and
a first layer, below the second layer, the first layer comprising third and fourth interdigitated capacitor electrodes, both parallel to and intersecting a second planar surface, the second planar surface parallel to and separated by a first non-zero distance from the first planar surface;

wherein the first set of coupling vias electrically couples the first electrode to the third electrode; wherein the second set of coupling vias that electrically couples the second electrode to the fourth electrode;
wherein the first layer further comprises insulative prepreg material, separating the third and fourth electrodes; wherein the third layer further comprises insulative prepreg material separating the first and second electrodes; wherein the insulative prepreg material is characterized by a second dielectric constant non-identical to the first dielectric constant.

2. The multilayer fringe capacitor of claim 1 , wherein capacitance resulting from coupling between the first and third electrodes and coupling between the second and fourth electrodes contributes less than one percent to the total capacitance.

3. The multilayer fringe capacitor of claim 1 , wherein the first and second interdigitated capacitor electrodes are passivated without the use of solder stop or solder mask material.

4. The multilayer fringe capacitor of claim 1 , wherein the multilayer fringe capacitor further comprises a fourth layer, directly above the third layer, the fourth layer comprising an insulative material covering the first and second electrodes; wherein the multilayer fringe capacitor further comprises a fifth layer, the fifth layer comprising an auxiliary electrode.

5. The multilayer fringe capacitor of claim 4 , wherein structure of the auxiliary electrode is defined by a removal of material; wherein the removal of material is simultaneous or in iteration with capacitance measurements of the multilayer fringe capacitor, such that the removal of material changes a capacitance of the multilayer fringe capacitor from an initial value to a desired value, different from the initial value.

6. The multilayer fringe capacitor of claim 5 , wherein the removal of material is performed by at least one of laser ablation, milling, and etching.

7. The multilayer fringe capacitor of claim 4 , wherein the auxiliary electrode is coupled to a variable AC bias; wherein the variable AC bias is changed to alter a capacitance of the multilayer fringe capacitor.

8. The multilayer fringe capacitor of claim 4 , wherein the auxiliary electrode is passivated without the use of solder stop or solder mask material.

9. The multilayer fringe capacitor of claim 1 , further comprising fifth and sixth interdigitated capacitor electrodes, both parallel to and intersecting a third planar surface, the third planar surface parallel to and separated by a second non-zero distance from the second planar surface and by a third non-zero distance from the first planar surface;
a third set of coupling vias that electrically couples the third electrode to the fifth electrode; and
a fourth set of coupling vias that electrically couples the fourth electrode to the sixth electrode;

wherein the multilayer fringe capacitor further comprises fifth and sixth layers; wherein the fifth layer, directly below the first layer, comprises the third and fourth sets of coupling vias; wherein the sixth layer, directly below the fifth layer, comprises the fifth and sixth electrodes.

10. The multilayer fringe capacitor of claim 9 , wherein the fifth layer further comprises insulative core material, characterized by the first dielectric constant, separating the third and fourth sets of vias.

11. The multilayer fringe capacitor of claim 9 , wherein the fifth layer further comprises insulative prepreg material separating the third and fourth sets of vias; wherein the insulative prepreg material is characterized by the second dielectric constant.

12. The multilayer fringe capacitor of claim 11 , wherein the fifth layer is of a same thickness as the second layer.

13. The multilayer fringe capacitor of claim 11 , wherein the fifth layer is thicker than the second layer.

14. A time delay filter comprising:
a substrate comprising a first isolative layer, the first isolative layer comprising a first surface and a second surface, the second surface substantially parallel to the first surface;
a resonator, comprising a capacitive element coupled to an inductive element, the inductive element comprising:
a first conductive region coupled to the first surface of the first isolative layer,
a second conductive region coupled to the second surface of the first isolative layer,
a first via that is electrically coupled to and extends between the first and second conductive region;
a second via that is electrically coupled to and extends between the first conductive region and a first portion of the capacitive element; and
a third via that is electrically coupled to and extends between the second conductive region and a second portion of the capacitive element; wherein the first conductive region, the first via, the second conductive region, the second via, the capacitive element, and the third via form a loop;

a first coupling point, electrically coupled to the first conductive region of the resonator; and
a second coupling point, electrically coupled to the second conductive region of the resonator;

wherein the capacitive element comprises:
first and second interdigitated capacitor electrodes, both parallel to and intersecting a third surface; wherein the first electrode defines a first capacitor region within the third surface and the second electrode defines a second capacitor region within the third surface;
third and fourth interdigitated capacitor electrodes, both parallel to and intersecting a fourth surface, the fourth surface parallel to and separated by a non-zero distance from the third surface; wherein the third electrode defines a third capacitor region within the fourth surface and the fourth electrode defines a fourth capacitor region within the fourth surface;
a first set of capacitor coupling vias that electrically couples the first electrode to the third electrode; and
a second set of capacitor coupling vias that electrically couples the second electrode to the fourth electrode.

15. The time delay filter of claim 14 , wherein the capacitive element has a total capacitance measured between a point on the first electrode and a point on the fourth electrode, wherein capacitance resulting from coupling between the first and third electrodes and coupling between the second and fourth electrodes contributes less than ten percent to the total capacitance.

16. The time delay filter of claim 14 , wherein the capacitive element comprises first, second, and third layers; wherein the first layer comprises the third and fourth electrodes; wherein the second layer, directly above the first layer, comprises the first and second sets of coupling vias; wherein the third layer, directly above the second layer, comprises the first and second electrodes; wherein the multilayer fringe capacitor further comprises

Assignees

• Kumu Networks Inc

Inventors

• Hahn Wilhelm Steffen
• Riddle Alfred
• Landi Ernie

Classifications

• H01G4/385

  Single unit multiple capacitors, e.g. dual capacitor in one coil · CPC title

• H01G9/008

  Terminals · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G11/82

  Fixing or assembling a capacitive element in a housing, e.g. mounting electrodes, current collectors or terminals in containers or encapsulations · CPC title