Variable gain amplifier

Patent metadata

Field	Value
Publication number	US-10447220-B2
Application number	US-201815914625-A
Country	US
Kind code	B2
Filing date	Mar 7, 2018
Priority date	Mar 7, 2018
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A variable gain amplifier circuit including a first amplifier, a second amplifier, and a variable capacitor connected in series between the first amplifier and the second amplifier is disclosed. As a gain of the variable gain amplifier circuit varies, the input impedance, output impedance, noise figure and third-order output intercept point (OIP3) of the variable gain amplifier circuit remain unchanged.

First claim

The invention claimed is:

1. A variable gain amplifier circuit comprising:
a first amplifier;
a second amplifier;
a variable capacitor connected in series between the first amplifier and the second amplifier;
a shunt feedback resistor; and
an emitter degeneration resistor,
wherein the shunt feedback resistor and the emitter degeneration resistor set at least one of an input impedance and a gain of the first amplifier.

2. The variable gain amplifier circuit of claim 1 , further comprising:
an input impedance of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the input impedance remains unchanged.

3. The variable gain amplifier circuit of claim 1 , further comprising:
an output impedance of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the output impedance remains unchanged.

4. The variable gain amplifier circuit of claim 1 , further comprising:
a noise figure of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the noise figure remains unchanged.

5. The variable gain amplifier circuit of claim 1 , further comprising:
a third-order output intercept point (OIP3) of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the OIP3 remains unchanged.

6. The variable gain amplifier circuit of claim 1 , wherein the first amplifier and the second amplifier are high reverse isolation amplifiers.

7. The variable gain amplifier circuit of claim 1 , wherein the first amplifier is a Darlington transistor pair and the second amplifier is a cascode amplifier.

8. The variable gain amplifier circuit of claim 1 , further comprising:
a buffer amplifier connected between the first amplifier and the second amplifier.

9. The variable gain amplifier circuit of claim 1 , further comprising:
a radio frequency (RF) signal voltage of the variable gain amplifier circuit; and
an input capacitance of the second amplifier; wherein the variable capacitor and the input capacitance of the second amplifier split the RF signal voltage based on the capacitance of the variable capacitor.

10. The variable gain amplifier of claim 1 , further comprising:
an output impedance of the first amplifier comprising a first real component; and
an input impedance of the second amplifier comprising a second real component; wherein a sum of the first real component and the second real component are greater than zero.

11. The variable gain amplifier circuit of claim 1 , further comprising:
at least one field effect transistor of the variable capacitor; and
a control voltage of the variable capacitor; wherein the control voltage varies to change the capacitance of the variable capacitor.

12. The variable gain amplifier circuit of claim 1 , further comprising:
a gain of the variable gain amplifier circuit;
at least one switching device of the variable capacitor; wherein the at least one switching device switches on and off to vary the gain of the variable gain amplifier circuit.

13. A variable gain differential amplifier circuit comprising:
a first amplifier connected to a first input terminal;
a second amplifier connected to a first output terminal;
a first voltage buffer amplifier connected between the first amplifier and the second amplifier;
a third amplifier connected to a second input terminal;
a fourth amplifier connected to a second output terminal;
a second voltage buffer amplifier connected between the third amplifier and the fourth amplifier;
a first variable capacitor connected in series between the first amplifier and the second amplifier;
a second variable capacitor connected in series between the third amplifier and the fourth amplifier;
a first mutually coupled tapped shunt peaking inductor; and
a second mutually coupled tapped shunt peaking inductor; wherein the first shunt peaking inductor and the second shunt peaking inductor reject common mode signals.

14. The variable gain amplifier circuit of claim 13 , further comprising:
an input impedance of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the input impedance remains unchanged.

15. The variable gain amplifier circuit of claim 13 , further comprising:
an output impedance of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the output impedance remains unchanged.

16. The variable gain amplifier circuit of claim 13 , further comprising:
a noise figure of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the noise figure remains unchanged.

17. The variable gain amplifier circuit of claim 13 , further comprising:
a third-order output intercept point (OIP3) of the variable gain amplifier circuit; and
a gain of the variable gain amplifier circuit; wherein when the gain of the variable gain amplifier circuit varies the OIP3 remains unchanged.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Krishnamurthi Kathiravan
• Flewelling Gregory M

Classifications

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03G1/0094

  using switched capacitors · CPC title

• H03F2200/408

  the output amplifying stage of an amplifier comprising three power stages · CPC title

• H03F2200/211

  the input of an amplifier can be attenuated by a continuously controlled transistor attenuator · CPC title

• H03F3/3435

  using Darlington amplifiers · CPC title