Amplifier having a switchable current bias circuit

Patent metadata

Field	Value
Publication number	US-10447208-B2
Application number	US-201715843922-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Dec 15, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A circuit having (A) a transistor; (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.

First claim

What is claimed is:

1. A circuit, comprising:
a transistor;
a bias circuit for setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit on a reference current bus; and
a bias current level controller, comprising:
a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and
current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and the reference current bus through a corresponding one of the plurality of switches, the bias level controller combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET of a corresponding one of the switches, the combined current providing the reference current fed to the bias circuit on the reference current bus.

2. A circuit, comprising:
an amplifier comprising:
a transistor having a source electrode and a drain electrode, one of the source electrode and the drain electrode being coupled a reference potential;

another one of the source electrode and drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal,
a bias circuit for setting a bias current for the amplifier, the bias current passing between the source electrode and the drain electrode of the amplifier, the bias current having a current level in accordance with a reference current fed to the bias circuit on a reference current bus; and
a bias current level controller, comprising:
a plurality of switches, each one of the switches comprising: a MOS FET and a GaN FET connected in a cascode configuration, the MOS FET and the GaN being coupled to the reference potential; and
a current switching circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and the reference current bus through a corresponding one of the plurality of switches, the bias current level controller combining currents produced by the plurality of current sources in response a corresponding one of a plurality of bits of a digital word fed to a gate of the MOS FET of a corresponding one of the plurality of current sources, the combined current providing the reference current fed to the bias circuit on the reference current bus.

3. The switchable current circuit recited in claim 1 wherein each one of the bits has a selected one of either a low voltage level or a high voltage level and wherein the voltage source has a voltage greater than the high voltage level.

4. A switchable current bias circuit for a transistor, comprising:
a plurality of N cascode configured switches, each one of the plurality of N cascode connected switches being fed by a corresponding bit of an N-bit digital word, each one of the switches comprising: a MOS FET and a GaN FET connected in a cascode configuration between ground and an output terminal, where N is an integer greater than 1;
a current source circuit comprising a plurality of N current sources, each one of the N current sources being connected to the output terminal of a corresponding one of the N cascode configured switches;
wherein each one of the N cascode configured switches controls an “on” or “off” condition of a corresponding one of the N current sources selectively in accordance with the bit fed to the such one of the N cascode configured switches;
wherein the current source circuit combines currents produced at outputs of the current source circuits in response to the “on” or the “off” condition, such combined currents being produced on an output bus; and an amplifier, such amplifier comprising:
the transistor; and
bias circuitry connected to the output bus and fed to the combined currents, such transistor being fed a bias current having a current level in accordance with the combined currents.

5. A switchable current bias circuit for a transistor, comprising:
a current switching circuit comprising:
a controller fed by a bias current control signal for producing an N-bit digital word, where N is an integer greater than one, representative of one of 2 N bias current levels selected by the control signal;
a plurality of N cascode configured switches, each one of the plurality of N cascode connected switches being fed by a corresponding bit of the N-bit digital word, each one of the switches comprising: a MOS FET and a GaN FET connected in a cascode configuration between ground and an output terminal;
a current source circuit comprising a plurality of N current sources, each one of the N current sources being connected to the output terminal of a corresponding one of the N cascode configured switches, each one of the N current sources being connected between a voltage supply bus and an output bus;
wherein each one of the N cascode configured switches controls an “on” or “off” condition of a corresponding one of the N current sources selectively in accordance with the N-bit digital control signal produced by the controller;
wherein the current source circuit combines currents produced at outputs of the current source circuits in response to the “on” or the “off” condition on the output, such combined currents being produced on the output bus; and

an amplifier, such amplifier comprising:
the transistor; and
bias circuitry connected to the output bus, the combined currents on the output bus setting a bias current for the transistor, such bias current passing to the transistor from a second voltage source, the bias current fed to the transistor having a current level in accordance with the combined currents on the output bus.

6. A circuit, comprising:
a transistor;
a bias circuit for setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit through a current reference bus; and
a bias current level controller, comprising:
a plurality of switches; and
current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and the reference current bus through and an output of a corresponding one of the plurality of switches, the current source circuitry combining currents produced by each one of the current sources in response a binary control signal fed a corresponding one of the plurality of switches, the combined current providing the reference current fed to the bias circuit on the reference current bus; and
wherein the binary control signal changes between a first range of voltages R 1 and a voltage at the output of each one of the switches changes between a second range of voltages R 2 , where R 2 is greater than R 1 .

7. The circuit recited in claim 6 wherein each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration.

Assignees

• Raytheon Co

Inventors

• Bettencourt John P
• Kaper Valery S
• Lardizabal Steven M

Classifications

• H03M1/742

  using current sources as quantisation value generators · CPC title

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F1/306

  in junction-FET amplifiers (H03F1/303, H03F1/305, H03F1/309 take precedence) · CPC title