Sealed cavity structures with a planar surface

Patent metadata

Field	Value
Publication number	US-10446643-B2
Application number	US-201815876727-A
Country	US
Kind code	B2
Filing date	Jan 22, 2018
Priority date	Jan 22, 2018
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

First claim

What is claimed:

1. A structure comprising a cavity formed in a substrate material, the cavity being covered with epitaxial material that has an upper planar surface, wherein the cavity comprises a trench which includes a curvature at its open end and which is under a transistor.

2. The structure of claim 1 , further comprising a trench which extends from the cavity to a surface of the substrate material, wherein the cavity is under the trench.

3. The structure of claim 1 , wherein the epitaxial material is a reflowed SiGe material and upper Si sealing layer.

4. The structure of claim 3 , further comprising a transistor formed on the upper planar surface of the Si sealing layer, above the cavity.

5. The structure of claim 1 , wherein the cavity is under a source region and a drain region of a gate structure on the planar surface.

6. The structure of claim 1 , wherein the cavity is under source and drain regions extending partially but not completely under the gate on the planar surface.

7. The structure of claim 1 , wherein the cavity is only under a gate structure on the planar surface.

8. The structure of claim 1 , wherein the cavity is under a gate structure on the planar surface and extends partially under source/drain regions of the gate structure.

9. The structure of claim 1 , wherein a depletion region under source/drain regions of a gate structure on the planar surface is intersected by the cavity.

10. The structure of claim 1 , wherein a triple well under the gate structure on the planar surface is intersected by the cavity.

11. The structure of claim 1 , further comprising a plurality of cavities which are merged together and which are formed under a sealing layer and which are parallel and/or perpendicular to gate structures.

12. A structure comprising:
a substrate material;
a cavity formed in the substrate which includes a trench having a curved edge portion at its upper end;
a first material within the trench which migrates to the upper end of the trench; and
a second material which covers the first material and which covers the trench, the second material having a planar surface,
wherein the first material is SiGe, the second material is Si material, the SiGe has a Ge concentration of about 5-30%, and after reflow, the SiGe has a top surface that is flat.

13. The structure of claim 12 , wherein the first material has characteristics that allow it to reflow during the deposition of the Si material.

14. The structure of claim 12 , further comprising a transistor formed on the planar surface of the second material.

15. A structure comprising:
a substrate material;
a cavity formed in the substrate which includes a trench having a curved edge portion at its upper end;
a first material within the trench which migrates to the upper end of the trench; and
a second material which covers the first material and which covers the trench, the second material having a planar surface;
a gate structure with a source region and a drain region, wherein the cavity is under one of:
only the source region and the drain region;
the source region and the drain region and extends under the gate structure;
only under the gate structure on the planar surface; and
the gate structure and extends partially under the source region and the drain region.

Assignees

• Globalfoundries Inc

Inventors

• Adusumilli Siva P
• Stamper Anthony K
• Schutz Laura J
• Luce Cameron E

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title