Semiconductor device and production method

Patent metadata

Field	Value
Publication number	US-10446596-B2
Application number	US-201615773707-A
Country	US
Kind code	B2
Filing date	Nov 11, 2016
Priority date	Nov 25, 2015
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

The present technology relates to a semiconductor device and a production method that enable noise reduction. A drain region and a source region provided in a predetermined region of a semiconductor substrate; a channel region provided between the drain region and the source region; and a gate electrode formed on the channel region are included. The channel region includes a first impurity diffusion region, and a second impurity diffusion region that is an impurity diffusion region of a same conductivity type as the first impurity diffusion region, and has an impurity concentration different from an impurity concentration of the first impurity diffusion region, and is formed at a substantially center part of the first impurity diffusion region. The present technology can be applied to a transistor that configures an imaging device, for example.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a drain region and a source region in a specific region of a semiconductor substrate;
a channel region between the drain region and the source region; and
a gate electrode above the channel region,
wherein the channel region includes
a first impurity diffusion region having a first impurity concentration, and
a second impurity diffusion region having a second impurity concentration, wherein
the first impurity diffusion region and the second impurity diffusion region have same conductivity type,
the second impurity concentration is different from the first impurity concentration,
the second impurity diffusion region is at a substantially center part of the first impurity diffusion region, and
the first impurity diffusion region is formed at both ends of the channel region so as to surround the second impurity diffusion region.

2. The semiconductor device according to claim 1 , wherein
the second impurity concentration is higher than the first impurity concentration.

3. The semiconductor device according to claim 1 , wherein
the second impurity concentration is one of greater than or equal to 1.25 times the first impurity concentration.

4. The semiconductor device according to claim 1 , wherein
the second impurity concentration is one of smaller than or equal to 2.8 times the first impurity concentration.

5. The semiconductor device according to claim 1 , wherein
the second impurity diffusion region having a strip shape along a gate length direction of a center part of the first impurity diffusion region.

6. The semiconductor device according to claim 1 , wherein
the second impurity diffusion region is formed in a scattered manner in a specific shape in a gate length direction or a gate width direction of a center part of the first impurity diffusion region.

7. The semiconductor device according to claim 1 , wherein
the second impurity diffusion region is of a specific shape at a center part of the first impurity diffusion region.

8. A semiconductor device, comprising:
a drain region and a source region in a specific region of a semiconductor substrate;
a channel region between the drain region and the source region; and
a gate electrode above the channel region, wherein
the channel region is an impurity diffusion region,
an impurity is doped in the impurity diffusion region such that an impurity concentration is highest at a center part in the channel region, and
the center part of the channel region is surrounded by remaining of the channel region having lower impurity concentration than the impurity concentration of the center part.

9. A method of manufacturing a semiconductor device, comprising:
forming a drain region and a source region in a specific region of a semiconductor substrate;
forming a channel region between the drain region and the source region; and
forming a gate electrode on the channel region,
wherein the channel region includes
a first impurity diffusion region having a first impurity concentration, and
a second impurity diffusion region having a second impurity concentration, wherein
the first impurity diffusion region and the second impurity diffusion region have same conductivity type,
the second impurity concentration is different from the first impurity concentration, and
the second impurity diffusion region is formed at a substantially center part of the first impurity diffusion region, and
the first impurity diffusion region is formed at both ends of the channel region so as to surround the second impurity diffusion region.

10. The method according to claim 9 , further comprising:
forming the first impurity diffusion region by forming a first mask opened in the channel region and doping an impurity; and
forming the second impurity diffusion region by forming a second mask opened in a strip shape in a gate length direction of the channel region and doping the impurity.

11. The method according to claim 9 , further comprising:
forming the first impurity diffusion region by forming a first mask opened in the channel region and doping an impurity; and
forming the second impurity diffusion region by forming a second mask including a specific shape opened in a scattered manner in a gate length direction or a gate width direction of the channel region and doping the impurity.

12. The method according to claim 9 , further comprising:
forming the first impurity diffusion region by forming a first mask opened in the channel region and doping an impurity; and
forming the second impurity diffusion region by forming a second mask including a specific shape opened at a center part of the channel region and doping the impurity.

13. The method according to claim 9 , further comprising:
forming the first impurity diffusion region and the second impurity diffusion region by forming a mask opened in the channel region and doping an impurity from an oblique direction.

14. The method according to claim 9 , further comprising:
doping an impurity such that an impurity concentration of the second impurity diffusion region is one of equal to or greater than 1.25 times an impurity concentration of the first impurity diffusion region.

15. The method according to claim 9 , further comprising:
doping an impurity such that an impurity concentration of the second impurity diffusion region is one of smaller than or equal to 2.8 times an impurity concentration of the first impurity diffusion region.

Assignees

• Sony Corp

Inventors

• Tonegawa Susumu

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L29/78

  Electricity · mapped topic

• H01L27/04

  Electricity · mapped topic