Transistor display panel, manufacturing method thereof, and display device including the same

Patent metadata

Field	Value
Publication number	US-10446591-B2
Application number	US-201715452602-A
Country	US
Kind code	B2
Filing date	Mar 7, 2017
Priority date	Apr 7, 2016
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.

First claim

What is claimed is:

1. A transistor display panel comprising:
a driving voltage line and a first electrode disposed on a substrate;
a semiconductor disposed on the substrate and overlapping the first electrode; and
an electrode layer overlapping the semiconductor, the electrode layer comprising a drain electrode, a gate electrode, and a source electrode;
wherein:
the semiconductor includes a source region, a drain region, and a channel region;
all areas of the source region, the drain region, and the channel region are disposed above and overlap the first electrode in a direction perpendicular to the substrate;
the first electrode and the semiconductor are connected through the source electrode; and
the first electrode is disposed between the substrate and the semiconductor.

2. The transistor display panel of claim 1 , wherein
the drain region and the driving voltage line are connected through the drain electrode.

3. The transistor display panel of claim 1 , wherein
the source region and the first electrode are connected through the source electrode.

4. The transistor display panel of claim 1 , wherein the drain electrode, the gate electrode, and the source electrode are disposed in the same layer.

5. The transistor display panel of claim 1 , wherein the first electrode and the driving voltage line are disposed in the same layer.

6. A transistor display panel comprising:
a driving voltage line and a first electrode disposed on a substrate;
a semiconductor disposed on the substrate and overlapping the first electrode; and
an electrode layer overlapping the semiconductor, the electrode layer comprising a drain electrode, a gate electrode, and a source electrode;
a first insulating layer covering the driving voltage line and the first electrode; and
a second insulating layer covering the semiconductor,
wherein:
the first electrode and the semiconductor are connected through the source electrode;
the first electrode is disposed between the substrate and the semiconductor;
the first insulating layer and the second insulating layer comprise a first contact hole connecting the first electrode and the source electrode and a second contact hole connecting the driving voltage line and the drain electrode; and
the second insulating layer comprises a third contact hole connecting the source region and the source electrode and a fourth contact hole connecting the drain region and the drain electrode.

7. The transistor display panel of claim 6 , wherein the second insulating layer is disposed on an entire surface of the substrate.

8. A display device comprising:
a driving voltage line and a first electrode disposed on a substrate;
a semiconductor disposed on the substrate and overlapping the first electrode;
an electrode layer overlapping the semiconductor, the electrode layer comprising a drain electrode, a gate electrode, and a source electrode; and
a pixel electrode disposed on the electrode layer,
wherein:
the first electrode and the semiconductor are connected through the source electrode; and
each of the pixel electrode and the first electrode is connected with the semiconductor through the source electrode; and
the first electrode is disposed between the substrate and the semiconductor.

9. The display device of claim 8 , further comprising:
a first capacitor electrode disposed on the substrate; and
a second capacitor electrode disposed on the first capacitor electrode,
wherein:
the first capacitor electrode is integrally connected with the first electrode; and
the second capacitor electrode is integrally connected with the gate electrode.

10. The display device of claim 8 , wherein:
the semiconductor comprises a drain region, a channel, and a source region;
the drain region and the driving voltage line are connected through the drain electrode; and
the source region and the first electrode are connected through the source electrode.

11. The display device of claim 8 , further comprising;
a first insulating layer covering the driving voltage line and the first electrode; and
a second insulating layer covering the semiconductor,
wherein:
the first insulating layer and the second insulating layer comprise a first contact hole connecting the first electrode and the source electrode and a second contact hole connecting the driving voltage line and the drain electrode; and
the second insulating layer comprises a third contact hole connecting the source region and the source electrode and a fourth contact hole connecting the drain region and the drain electrode.

Assignees

• Samsung Display Co Ltd

Inventors

• Kwon Hyuk Soon

Classifications

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/13624

  having more than one switching element per pixel · CPC title

• G02F2201/123

  pixel · CPC title