Nonvolatile storage element and reference voltage generation circuit

Patent metadata

Field	Value
Publication number	US-10446567-B2
Application number	US-201815925023-A
Country	US
Kind code	B2
Filing date	Mar 19, 2018
Priority date	Mar 31, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.

First claim

The invention claimed is:

1. A reference voltage generation circuit comprising:
a first MOS transistor including a first source terminal, a first drain terminal, and a first gate terminal in a floating state;
a second MOS transistor including a second gate terminal connected to the first gate terminal, a second source terminal, a second drain terminal, and a second bulk terminal, the second source terminal, the second drain terminal, and the second bulk terminal being connected to the first source terminal and being connected to each other;
a third MOS transistor including a third source terminal, a third drain terminal, and a third gate terminal in a floating state;
a fourth MOS transistor including a fourth gate terminal connected to the third gate terminal, a fourth source terminal, a fourth drain terminal, and a fourth bulk terminal, the fourth source terminal, the fourth drain terminal, and the fourth bulk terminal being connected to the third drain terminal and being connected to each other;
a first power source terminal; and
a second power source terminal configured to have a lower voltage than a voltage of the first power source terminal when the first MOS transistor and the third MOS transistor are N-channel MOS transistors, and to have a higher voltage than the voltage of the first power source terminal when the first MOS transistor and the third MOS transistor are P-channel MOS transistors,
wherein the first drain terminal is connected to the first power source terminal, the third source terminal is connected to the second power source terminal, and the first source terminal is connected to the third drain terminal; or
wherein the third drain terminal is connected to the first power source terminal, the first source terminal is connected to the second power source terminal, and the first drain terminal is connected to the third source terminal.

2. The reference voltage generation circuit according to claim 1 , wherein the first MOS transistor and the second MOS transistor serve as a single depletion type MOS transistor, and the third MOS transistor and the fourth MOS transistor serve as a single enhancement type MOS transistor.

3. The reference voltage generation circuit according to claim 1 , wherein the first MOS transistor and the third MOS transistor are of the same conductive type.

4. The reference voltage generation circuit according to claim 1 , wherein an area of each of the second MOS transistor and the fourth MOS transistor is from 1000 μm 2 to 1 mm 2 .

5. The reference voltage generation circuit according to claim 1 , wherein the first to fourth MOS transistors do not have any array structure.

6. A nonvolatile storage element comprising:
a first MOS transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in a floating state;
a second MOS transistor including a second gate, a second source region, a second drain region, and a second bulk region, the second gate being of another conductive type of P type or N type, the second source region, the second drain region, and the second bulk region being connected to each other;
a PN junction portion configured to form a PN junction between the first gate and the second gate; and
a silicide formed on the PN junction portion, wherein
the nonvolatile storage element includes at least one of a structure in which the conductivity type of the first gate is different from a conductivity type of the first source region in the first MOS transistor, and a structure in which the conductivity type of the second gate is different from a conductivity type of the second source region in the second MOS transistor.

7. A nonvolatile storage element comprising:
a first MOS transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in a floating state;
a second MOS transistor including a second gate, a second source region, a second drain region, and a second bulk region, the second gate being of another conductive type of P type or N type, the second source region, the second drain region, and the second bulk region being connected to each other;
a PN junction portion configured to form a PN junction between the first gate and the second gate;
a silicide formed on the PN junction portion; and
a third MOS transistor including a third gate connected to the second gate, a third source region, a third drain region, and a third bulk region, the third gate being of the other conductive type, the third source region, the third drain region, and the third bulk region being connected to each other, wherein
the nonvolatile storage element includes at least one of a structure in which the conductivity type of the first gate is different from a conductivity type of the first source region in the first MOS transistor, a structure in which the conductivity type of the second gate is different from a conductivity type of the second source region in the second MOS transistor, and a structure in which the conductivity type of the third gate is different from a conductivity type of the third source region in the third MOS transistor.

8. A reference voltage generation circuit comprising a plurality of nonvolatile storage elements each of which comprising:
a first MOS transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in a floating state;
a second MOS transistor including a second gate, a second source region, a second drain region, and a second bulk region, the second gate being of another conductive type of P type or N type, the second source region, the second drain region, and the second bulk region being connected to each other;
a PN junction portion configured to form a PN junction between the first gate and the second gate; and
a silicide formed on the PN junction portion,
the plurality of the nonvolatile storage elements including at least a first nonvolatile storage element configured to serve as a depletion type MOS transistor and a second nonvolatile storage element configured to serve as an enhancement type MOS transistor, and
the first nonvolatile storage element and the second nonvolatile storage element being connected in series between a first power source terminal and a second power source terminal.

9. The reference voltage generation circuit according to claim 8 , wherein at least one of the first gate and the second gate of the first nonvolatile storage element is of a different conductive type from the conductive type of at least one of the first gate and the second gate of the second volatile storage element in at least some regions.

10. The reference voltage generation circuit according to claim 8 , wherein the first nonvolatile storage element is the same in size as the second nonvolatile storage element.

11. The reference voltage generation circuit according to claim 8 , wherein an area of each of the first nonvolatile storage element and the second nonvolatile storage element is from 1000 μm 2 to 1 mm 2 .

12. The reference voltage generation circuit according to claim 8 , wherein the first nonvolatile storage element and the second nonvolatile storage element do not have any array structure.

13. A reference voltage generation circuit comprising a plurality of nonvolatile storage elements each of which comprising:
a first MOS transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in

Assignees

• Asahi Kasei Microdevices Corp

Inventors

• Sakamoto Toshiro
• Takehara Satoshi

Classifications

• G05F3/247

  producing a voltage or current as a predetermined function of the supply voltage · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G05F3/245

  producing a voltage or current as a predetermined function of the temperature · CPC title

• G04G19/06

  Regulation · CPC title

• G11C16/0416

  comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM · CPC title