Isolation between semiconductor components

Patent metadata

Field	Value
Publication number	US-10446498-B2
Application number	US-201715676360-A
Country	US
Kind code	B2
Filing date	Aug 14, 2017
Priority date	Jan 10, 2014
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

First claim

What is claimed is:

1. An apparatus comprising:
a first semiconductor die;
a second semiconductor die; and
a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die, the capacitive isolation circuit being disposed outside of the first semiconductor die and the second semiconductor die,
the first semiconductor die, the second semiconductor die, and the capacitive isolation circuit being included in a molding of a semiconductor package,
the capacitive isolation circuit including:
a first capacitor network having first and second conductive layers with a dielectric material disposed between the first and second conductive layers, the first capacitor network being coupled to the first semiconductor die;
a second network capacitor having first and second conductive layers with a dielectric material disposed between the first and second conductive layers, the second capacitor network being coupled to the second semiconductor die; and
a bond wire coupled to at least one of the first capacitor network and the second capacitor network.

2. The apparatus of claim 1 , wherein the capacitive isolation circuit defines a distance through insulation that is at least twice a thickness of the dielectric material of either the first capacitor network or the second capacitor network, the twice the thickness being greater than or equal to a distance between a first lead frame portion and a second lead frame portion.

3. The apparatus of claim 1 , wherein the bond wire is a first bond wire, the apparatus further comprising:
a second bond wire coupled to the first semiconductor die and a first lead frame portion.

4. The apparatus of claim 3 , further comprising:
a third bond wire coupled to the second semiconductor die and a second lead frame portion.

5. The apparatus of claim 1 , further comprising:
a first lead frame coupled to the first semiconductor die; and
a second lead frame coupled to the second semiconductor die, the second lead frame being disposed apart from the first lead frame.

6. The apparatus of claim 1 , wherein the first semiconductor die is coupled to the first capacitor network via one or more solder balls, and the second semiconductor die is coupled to the second capacitor network via one or more solder components.

7. The apparatus of claim 1 , wherein the first semiconductor die is coupled to the first capacitor network via a conductive epoxy, and the second semiconductor die coupled to the second capacitor network via a conductive epoxy.

8. The apparatus of claim 1 , wherein the second conductive layer of the first capacitor network has a length different from a length of the first conductive layer of the first capacitor network.

9. The apparatus of claim 1 , wherein the second conductive layer of the first capacitor network has a length that is the same as a length of the first conductive layer of the first capacitor network.

10. The apparatus of claim 1 , wherein the bond wire includes a first end portion that is coupled to the first capacitor network and a second end portion that is coupled to the second capacitor network.

11. The apparatus of claim 1 , further comprising:
a third capacitor network having first and second conductive layers with a dielectric material disposed between the first and second conductive layers.

12. The apparatus of claim 11 , wherein the bond wire has a first end portion that is coupled to the first capacitor network and a second end portion that is coupled to the third capacitor network.

13. An apparatus comprising:
a first semiconductor die having a first surface and a second surface disposed opposite to the first surface;
a second semiconductor die having a first surface and a second surface disposed opposite to the first surface;
a first lead frame portion coupled to the second surface of the first semiconductor die;
a second lead frame portion coupled to the second surface of the second semiconductor die, the first and second lead frame portions being portions on a same lead frame or the first and second lead frame portions each being on different lead frames;
a first capacitor network coupled to the first surface of the first semiconductor die via one or more first conductive components; and
a second capacitor network coupled to the first surface of the second semiconductor die via one or more second conductive components.

14. The apparatus of claim 13 , further comprising:
a bond wire coupled to the first capacitor network and the second capacitor network.

15. The apparatus of claim 13 , wherein each of the first capacitor network and the second capacitor network includes first and second conductive layers with a dielectric material disposed between the first and second conductive layers.

16. The apparatus of claim 13 , further comprising:
a third lead frame portion that is separate from the first lead frame portion and the second lead frame portion; and
a third capacitor network coupled to the third lead frame portion.

17. The apparatus of claim 13 , further comprising:
a first bond wire coupled to the first surface of the first semiconductor die and the first lead frame portion; and
a second bond wire coupled to the first surface of the second semiconductor die and the second lead frame portion.

18. An apparatus comprising:
a first semiconductor die having a first surface and a second surface disposed opposite to the first surface;
a second semiconductor die having a first surface and a second surface disposed opposite to the first surface;
a first lead frame portion coupled to the second surface of the first semiconductor die;
a second lead frame portion coupled to the second surface of the second semiconductor die, the first and second lead frame portions being portions on a same lead frame or the first and second lead frame portions each being on different lead frames;
a first capacitor network coupled to the first surface of the first semiconductor die via one or more first conductive components;
a second capacitor network coupled to the first surface of the second semiconductor die via one or more second conductive components, each of the first capacitor network and the second capacitor network includes first and second conductive layers with a dielectric material disposed between the first and second conductive layers;
a first bond wire coupled to the first capacitor network and the second capacitor network;
a second bond wire coupled to the first surface of the first semiconductor die and the first lead frame portion; and
a third bond wire coupled to the first surface of the second semiconductor die and the second lead frame portion.

Assignees

• Fairchild Semiconductor

Inventors

• Constantino John
• Luk Timwah
• Ashrafzadeh Ahmad
• Krause Robert L
• Shacham Etan
• Quinones Maria Clemens Ypil
• Bryzek Janusz
• Wu Chung-Lin

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/738

  between a chip and a stacked discrete passive device · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title