Multilayer printed circuit board via hole registration and accuracy

Patent metadata

Field	Value
Publication number	US-10446356-B2
Application number	US-201715784070-A
Country	US
Kind code	B2
Filing date	Oct 13, 2017
Priority date	Oct 13, 2016
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

First claim

What is claimed is:

1. A method of making accurate multilayer printed circuit hole to conductive feature geometry, comprising:
drilling a first hole in a first core, the first hole having a first diameter;
filling and/or plating the first hole with a first electrically conductive material;
forming a circuit pattern on one or two conductive layers of the first core;
forming a second core including a first pre-drilled via hole filled and/or plated with a second electrically conductive material;
combining the first core and the second core to form a multilayer structure with the first hole of the first core misaligned with the first pre-drilled via hole of the second core;
drilling a second hole within the first hole and the first pre-drilled via hole, the second hole having a second diameter where the second diameter is smaller than the first diameter; and
plating a third electrically conductive material to an inner surface of the second hole to form a plated through hole extending through the first core and the second core, wherein a plating thickness of the conductive material plated to the inner surface of the second hole is at least 10 micron (0.0004″).

2. The method of claim 1 , further comprising:
forming a circuit pattern on one or both outer conductive layers of the multilayer structure.

3. The method of claim 1 , further comprising:
adding alignment mark holes to the printed circuit board contemporaneously with drilling the first hole.

4. The method of claim 3 , wherein the alignment mark holes are protected from being filled or plated with electrical conductive material.

5. The method of claim 1 , wherein at least one of the first electrically conductive material, the second electrically conductive material, or the third electrically conductive material is copper plating, conductive material fill, or both.

6. The method of claim 1 , where the second drill diameter is smaller than the first drill diameter by at least 10 micron (0.0004″).

7. A multilayer printed circuit structure manufactured by the process comprising the steps of:
drilling a first hole in a first core, the first hole having a first diameter;
filling and/or plating the first hole with a first electrically conductive material;
forming a circuit pattern on one or two conductive layers of the first core;
forming a second core including a first pre-drilled via hole filled and/or plated with a second electrically conductive material;
combining the first core and the second core to form a multilayer structure with the first hole of the first core misaligned with the first pre-drilled via hole of the second core;
drilling a second hole within the first hole and the first pre-drilled via hole, the second hole having a second diameter where the second diameter is smaller than the first diameter; and
plating a third electrically conductive material to an inner surface of the second hole to form a plated through hole extending through the first core and the second core, wherein a plating thickness of the third electrically conductive material is at least 10 micron (0.0004″).

8. The multilayer printed circuit structure manufactured by the process of claim 7 , further comprising the step of:
forming a circuit pattern on one or both outer conductive layers of the multilayer structure.

9. The multilayer printed circuit structure manufactured by the process of claim 7 , further comprising the step of:
adding alignment mark holes to the printed circuit board contemporaneously with drilling the first hole.

10. The multilayer printed circuit structure manufactured by the process of claim 9 , wherein the alignment mark holes are protected from being filled or plated with electrical conductive material.

11. The method of claim 1 , wherein:
forming the circuit pattern on one or two conductive layers of the first core comprises forming a circuit pattern on one or two conductive layers of the first core, the circuit pattern including a first conductive feature a first distance from the first hole;
forming the second core further comprises forming the second core including a second conductive feature a second distance from the first pre-drilled via hole; and
where the formed plated through hole maintains the first distance from first conductive feature and the second distance from the second conductive feature.

12. The multilayer printed circuit structure manufactured by the process of claim 7 , wherein:
forming the circuit pattern on one or two conductive layers of the first core comprises forming a circuit pattern on one or two conductive layers of the first core, the circuit pattern including a first conductive feature a first distance from the first hole;
forming the second core further comprises forming the second core including a second conductive feature a second distance from the first pre-drilled via hole; and
where the formed plated through hole maintains the first distance from first conductive feature and the second distance from the second conductive feature.

Assignees

• Sanmina Corp

Inventors

• Iketani Shinichi
• Thomas Douglas Ward

Classifications

• H05K3/4623

  the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards (H05K3/462 takes precedence) · CPC title

• H05K3/4638

  Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits · CPC title

• H05K2201/041

  Stacked PCBs, i.e. having neither an empty space nor mounted components in between · CPC title

• H01H85/06

  characterised by the fusible material (H01H85/11 takes precedence) · CPC title

• H05K2201/09536

  Buried plated through-holes, i.e. plated through-holes formed in a core before lamination · CPC title