Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10446204-B2
Application number	US-201715702298-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Mar 22, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first memory cell including a first resistance change memory element and a first transistor;
a first word line electrically coupled to a control terminal of the first transistor; and
a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period,
wherein the first circuit includes:
a second transistor having a first terminal to which the first voltage is supplied, a second terminal electrically coupled to the first word line, and a control terminal to which a first signal is supplied;
a third transistor having a first terminal to which the second voltage is supplied, a second terminal electrically coupled to the first word line, and a control terminal to which a second signal is supplied;
an OR gate having a first input terminal to which a third signal is input and a second input terminal to which the delayed and inverted third signal is input, and configured to output the first signal; and
a NAND gate having a first input terminal to which the inverted third signal is input and a second input terminal to which the inverted and delayed third signal is input, and configured to output the second signal.

2. The device of claim 1 , wherein the first circuit further includes:
a second circuit configured to output the first signal so as to turn on the second transistor during the first period; and
a third circuit configured to output the second signal so as to turn on the third transistor during the second period.

3. The device of claim 1 , further comprising:
a sense amplifier electrically coupled to the first memory cell; and
a fourth transistor electrically coupled between the first memory cell and the sense amplifier,
wherein a third voltage is applied to a control terminal of the fourth transistor before the first period, and a fourth voltage higher than the third voltage is applied to the control terminal of the fourth transistor during the first period.

4. The device of claim 3 , wherein the fourth voltage is generated by coupling between the control terminal of the fourth transistor and a first terminal of the fourth transistor.

5. The device of claim 3 , further comprising:
a fourth circuit configured to apply the fourth voltage to the control terminal of the fourth transistor.

6. A semiconductor memory device comprising:
a first memory cell including a first resistance change memory element;
a sense amplifier electrically coupled to the first memory cell;
a first transistor electrically coupled between the first memory cell and the sense amplifier;
a first control line electrically coupled to a control terminal of the first transistor; and
a first circuit configured to, in a reading, apply a first voltage to the first control line during a first period and apply a second voltage higher than the first voltage to the first control line during a second period after the first period,
wherein the first circuit includes:
a third transistor having a first terminal to which the first voltage is supplied, a second terminal electrically coupled to the first control line, and a control terminal to which a first signal is supplied;
a fourth transistor having a first terminal to which the second voltage is supplied, a second terminal electrically coupled to the first control line, and a control terminal to which a second signal is supplied;
an OR gate having a first input terminal to which a third signal is input and a second input terminal to which the delayed and inverted third signal is input, and configured to output the first signal; and
a NAND gate having a first input terminal to which the inverted third signal is input and a second input terminal to which the inverted and delayed third signal is input, and configured to output the second signal.

7. The device of claim 6 , further comprising:
a sink electrically coupled to the first memory cell;
a second transistor electrically coupled between the first memory cell and the sink; and
a second control line electrically coupled to a control terminal of the second transistor.

8. The device of claim 7 , wherein control signals for executing a same operation are supplied to the first control line and the second control line, respectively.

9. The device of claim 6 , wherein the first circuit further includes:
a second circuit configured to output the first signal so as to turn on the third transistor during the first period; and
a third circuit configured to output the second signal so as to turn on the fourth transistor during the second period.

10. The device of claim 6 , further comprising:
a fifth transistor electrically coupled between the first transistor and the sense amplifier,
wherein a third voltage is applied to a control terminal of the fifth transistor before the first period, and a fourth voltage higher than the third voltage is applied to the control terminal of the fifth transistor during the first period.

11. The device of claim 10 , wherein the fourth voltage is generated by coupling between the control terminal of the fifth transistor and a first terminal of the fifth transistor.

12. The device of claim 10 , further comprising:
a fourth circuit configured to apply the fourth voltage to the control terminal of the fifth transistor.

13. A semiconductor memory device comprising:
a first memory cell including a first resistance change memory element and a first transistor;
a first word line electrically coupled to a control terminal of the first transistor; and
a first circuit including:
a second transistor with a first terminal to which a first voltage is supplied, a second terminal electrically coupled to the first word line, and a control terminal to which a first signal is supplied;
a third transistor with a first terminal to which a second voltage is supplied, a second terminal electrically coupled to the first word line, and a control terminal to which a second signal is supplied;
an OR gate having a first input terminal to which a third signal is input and a second input terminal to which the delayed and inverted third signal is input, and configured to output the first signal; and
a NAND gate having a first input terminal to which the inverted third signal is input and a second input terminal to which the inverted and delayed third signal is input, and configured to output the second signal.

14. The device of claim 13 , wherein the first circuit further includes:
a second circuit configured to output the first signal so as to turn on the second transistor during a first period; and
a third circuit configured to output the second signal so as to turn on the third transistor during a second period after the first period.

15. The device of claim 1 , wherein the second period is longer than the first period.

Assignees

• Toshiba Memory Corp

Inventors

• Inaba Tsuneo

Classifications

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/15 Primary

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C11/1653 Primary

  Address circuits or decoders · CPC title