Voltage generation circuit

Patent metadata

Field	Value
Publication number	US-10446195-B2
Application number	US-201615312010-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jun 29, 2016
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.

First claim

The invention claimed is:

1. An apparatus, comprising:
a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage;
a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor;
an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage;
a feedback circuit stage coupled to the first biasing circuit stage and to the voltage generation circuit stage through the biasing signal line; and
a gate voltage line that provides a further coupling between the feedback circuit stage and the voltage generation circuit stage;
wherein the feedback circuit stage provides a pull-up signal to the voltage generation circuit stage via the gate voltage line responsive to an increased current in the feedback circuit stage, the increased current in the feedback circuit stage corresponding to a decreased current in the voltage generation circuit stage that occurs due to a pull-down load current at the output line.

2. The apparatus of claim 1 , wherein the voltage generation circuit stage further comprises:
a pull-up transistor coupled between a power supply voltage and the output transistor and coupled to the feedback circuit stage through the gate voltage line, the gate voltage line being coupled to a gate terminal of the pull-up transistor;
wherein a pull-up ability of the pull-up transistor increases responsive to the pull-up signal provided by the feedback circuit stage so as to raise the output voltage back towards the steady-state voltage responsive to a drop in the output voltage that corresponds to the pull-down load current at the output voltage.

3. The apparatus of claim 1 , wherein the feedback circuit stage comprises:
a resistor coupled at a first end to a power supply voltage; and
a transistor coupled to a second end of the resistor;
wherein the gate voltage line is output from the feedback circuit stage through a circuit node that couples the resistor to the transistor in the feedback circuit stage.

4. The apparatus of claim 3 , further comprising:
a voltage reference line that provides a further coupling between the feedback circuit stage and the voltage generation circuit stage;
wherein the feedback circuit stage provides a pull-down signal to the voltage generation circuit stage via the voltage reference line responsive to an increased voltage on the voltage reference line, the increased voltage on the voltage reference line corresponding to an increased current in the voltage generation circuit stage that occurs due to a pull-up load current at the output line.

5. The apparatus of claim 4 , wherein the voltage reference line is coupled to the feedback circuit stage through a coupling to a drain terminal of the transistor associated with the feedback circuit stage.

6. The apparatus of claim 4 , wherein the voltage generation circuit further comprises:
a pull-down transistor coupled between the output line and ground, the pull-down transistor further coupled to the feedback circuit stage and to the output transistor through the voltage reference line, the voltage reference line being coupled to a gate terminal of the pull-down transistor, a drain terminal of the output transistor coupled to the voltage reference line;
wherein a pull-down ability of the pull-down transistor increases responsive to the pull-down signal provided by the feedback circuit stage so as to lower the output voltage back towards the steady-state voltage responsive to a rise in the output voltage that corresponds to the pull-up load current at the output voltage.

7. The apparatus of claim 4 , further comprising:
a second biasing circuit stage coupled to the feedback circuit stage and to the voltage generation stage through a voltage reference line;
wherein the second biasing circuit stage is configured to generate currents in the feedback circuit stage and the voltage generation stage corresponding to a current in the first biasing circuit stage.

8. The apparatus of claim 7 , wherein the second biasing circuit stage comprises:
a first current mirror branch coupled to the first biasing circuit stage and configured to provide a current corresponding to the current in the first biasing circuit stage; and
a second current mirror branch coupled to the feedback circuit stage and to the voltage generation circuit stage, the second current mirror branch configured to provide twice the current present in the first current mirror branch.

9. A method, comprising:
providing a biasing voltage from a first biasing circuit stage based on a current through a first resistor associated with the first biasing circuit stage;
receiving the biasing voltage signal at a voltage generation circuit stage through a biasing signal line that is coupled to a gate terminal of an output transistor that is associated with the voltage generation circuit stage;
generating an output voltage from the voltage generation circuit stage based on the biasing voltage provided by the biasing circuit stage, the output voltage having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage; and
providing the output voltage to a load so as to control a gate-induced drain leakage current in the load;
generating a pull-up signal at a feedback circuit stage responsive to an increased current in the feedback circuit stage, wherein the increased current in the feedback circuit stage corresponds to a decreased current in the voltage generation circuit stage that occurs due to a pull-down load current at the output line;
receiving the pull-up signal at a gate terminal of a pull-up transistor associated with the voltage generation circuit stage, the pull-up signal being received across a gate voltage line that couples the feedback circuit stage to the voltage generation stage; and
increasing a pull-up ability of the pull-up transistor responsive to the pull-up signal provided by the feedback circuit stage so as to raise the output voltage back towards the steady-state voltage responsive to a drop in the output voltage that corresponds to the pull-down load current at the output line.

10. The method of claim 9 , further comprising:
providing current to the first resistor through a biasing transistor coupled between a power supply voltage and a first end of the first resistor, wherein a voltage drop across the biasing transistor substantially cancels a voltage drop across the output transistor in the output voltage provided on the output line by the voltage generation circuit stage.

11. The method of claim 9 , further comprising:
varying a resistance of the first resistor so as to cause a corresponding variation in the output voltage provided on the output line by the voltage generation circuit stage.

12. The method of claim 9 , further comprising:
generating a pull-down signal at a feedback circuit stage responsive to an increased voltage on a voltage reference that couples the feedback circuit stage to the voltage generation stage, wherein the increased voltage on the voltage reference line corresponds to an increased current in the voltage generat

Assignees

• Micron Technology Inc

Inventors

• Pan Dong
• Wu Jun

Classifications

• G11C29/021

  in voltage or current generators · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title