Display device

Patent metadata

Field	Value
Publication number	US-10446076-B2
Application number	US-201615367599-A
Country	US
Kind code	B2
Filing date	Dec 2, 2016
Priority date	Dec 21, 2015
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A display device related to one embodiment of the present invention includes a plurality of pixel circuits each connected to a scanning signal line, initialization control signal line, light emitting control signal line and video signal line, wherein each of the plurality of pixel circuits includes a first transistor connected to the scanning signal line and the video signal line, a second transistor connected to a first node and the first transistor, a third transistor connected to the first node and a scanning signal line, a fourth transistor connected to the second transistor and the light emitting control signal line, and a fifth transistor connected to the second transistor, a power supply voltage line, and the light emitting control signal line.

First claim

What is claimed is:

1. A display device comprising:
a plurality of first scanning signal lines;
a plurality of second scanning signal lines;
a plurality of initialization control signal lines;
a plurality of light emitting control signal lines;
a plurality of video signal lines arranged intersecting the plurality of first scanning signal lines, the plurality of second scanning signal lines, the plurality of initialization control signal lines, and the plurality of light emitting control signal lines; and
a plurality of pixel circuit groups each connected to one of the first scanning signal lines, one of the second scanning signal lines, one of the initialization control signal lines, one of the light emitting control signal lines, and one of the video signal lines;
wherein
each of the plurality of pixel circuit groups includes
a first pixel circuit;
a second pixel circuit;
a first transistor including a control terminal connected to the light emitting control signal line, a first terminal connected to a power supply voltage line, and a second terminal; and
a fifth transistor including a control terminal connected to the first scanning signal line, a first terminal connected to the video signal line, and a second terminal;
the first pixel circuit includes:
a second transistor including a control terminal connected to a first node, a first terminal connected to the second terminal of the first transistor and the second terminal of the fifth transistor, and a second terminal;
a third transistor including a first terminal connected to the first node, a second terminal connected to the second terminal of the second transistor, and a control terminal connected to the second scanning signal line;
a fourth transistor including a first terminal connected to the second terminal of the second transistor, a second terminal, and a control terminal connected to the light emitting control signal line;
a storage capacitor including a first terminal connected to the first node, and a second terminal connected to the initialization control signal line; and
a light emitting element connected to the second terminal of the fourth transistor, and

the second pixel circuit includes:
another second transistor including a control terminal connected to another first node, a first terminal connected to the second terminal of the first transistor and the second terminal of the fifth transistor, and a second terminal;
another third transistor including a first terminal connected to the another first node, a second terminal connected to the second terminal of the another second transistor, and a control terminal connected to the second scanning signal line;
another fourth transistor including a first terminal connected to the second terminal of the another second transistor, a second terminal, and a control terminal connected to the light emitting control signal line;
another storage capacitor including a first terminal connected to the another first node, and a second terminal connected to the initialization control signal line; and
another light emitting element connected to the second terminal of the another fourth transistor.

2. The display device according to claim 1 , further comprising:
a drive circuit outputting a signal to the first scanning signal line, the second scanning signal line, the initialization control signal line, the light emitting control signal line, and the video signal line;
wherein
the drive circuit supplies a signal to the control terminal of the third transistor to turn the third transistor OFF in an initialization period; and
the drive circuit changes a voltage of the second terminal of the storage capacitor by changing the initialization control signal line to a first voltage so that the third transistor changes to ON in the initialization period.

3. The display device according to claim 2 , wherein the drive circuit changes a voltage of the second terminal of the storage capacitor by changing the initialization control signal line to a second voltage lower than the first voltage in a writing and threshold compensation period after the initialization period, the drive circuit turns the third transistor to ON in sequence and supplies gradation data in sequence to the video signal line in a state where a signal for turning the fifth transistor to ON is supplied to the first scanning signal line in the writing and threshold compensation period.

4. The display device according to claim 3 , wherein the drive circuit changes the first transistor and fourth transistor to ON in light emitting period after the writing and threshold compensation period in a state where a signal for turning the third transistor and fifth transistor to OFF is supplied to the first scanning signal line, and the drive circuit supplies a current to the light emitting element to emit light from the light emitting element in the light emitting period.

5. The display device according to claim 1 , wherein the first to fifth transistors are transistors having the same polarity.

6. The display device according to claim 5 , wherein the first to fifth transistors are P channel transistors.

7. The display device according to claim 1 , wherein
a number of the first scanning lines is less than a number of the second scanning lines,
a number of the initialization control signal lines is less than the number of the second scanning lines, and
a number of the light emitting control signal lines is less than the number of the second scanning lines.

Assignees

• Japan Display Inc

Inventors

• Wu Ilin

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2320/0271

  Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title