Fault buffer for resolving page faults in unified virtual memory system

Patent metadata

Field	Value
Publication number	US-10445243-B2
Application number	US-201314055356-A
Country	US
Kind code	B2
Filing date	Oct 16, 2013
Priority date	Mar 14, 2013
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

First claim

What we claim is:

1. A system for resolving page faults with a fault buffer, the system comprising:
a fault buffer configured to store a plurality of fault buffer entries, wherein a first fault buffer entry included in the plurality of fault buffer entries is associated with a first page fault generated by a first processor;
a second processor that executes a first fault handler to:
read the first fault buffer entry associated with the first page fault, and
trigger a first page fault sequence to resolve the first page fault, wherein the first page fault sequence includes executing at least one command by a copy engine included in the first processor; and

a second fault handler executed by the second processor, wherein the second fault handler is configured to resolve a second page fault generated by the second processor, and the second fault handler is configured to resolve the second page fault generated by the second processor without transmitting any fault buffer entries associated with the second page fault to the fault buffer.

2. The system of claim 1 , wherein the first page fault is associated with a first process, and the second processor executes the first fault handler to read the first fault buffer entry and trigger the first page fault sequence while the first processor executes work associated with a second process.

3. The system of claim 1 , wherein the second processor comprises a central processing unit.

4. The system of claim 1 , wherein the second processor executes the first fault handler to transmit the at least one command to a command queue associated with the copy engine during the first page fault sequence.

5. The system of claim 4 , wherein the at least one command causes the copy engine to update a first page table associated with the first processor to include a first mapping associated with the first page fault.

6. The system of claim 1 , wherein the first processor includes a first streaming multiprocessor configured to execute a first thread associated with a first process, wherein the first thread causes the first page fault to be generated.

7. The system of claim 6 , wherein the first fault buffer entry includes an indication of an address space that is associated with the first page fault and with the first process.

8. A computing device for resolving page faults with a fault buffer, the computing device, comprising:
a first processor that comprises a copy engine;
a fault buffer configured to store a plurality of fault buffer entries, wherein a first fault buffer entry included in the plurality of fault buffer entries is associated with a first page fault generated by the first processor;
a second processor that executes a first fault handler to:
read the first fault buffer entry associated with the first page fault, and
trigger a first page fault sequence to resolve the first page fault, wherein the first page fault sequence includes executing at least one command by the copy engine included in the first processor; and

a second fault handler executed by the second processor, wherein the second fault handler is configured to resolve a second page fault generated by the second processor, and the second fault handler is configured to resolve the second page fault generated by the second processor without transmitting any fault buffer entries associated with the second page fault to the fault buffer.

9. The computing device of claim 8 , wherein the first page fault is associated with a first process, and the second processor executes the first fault handler to read the first fault buffer entry and trigger the first page fault sequence while the first processor executes work associated with a second process.

10. The computing device of claim 8 , wherein the second processor comprises a central processing unit.

11. The computing device of claim 8 , wherein the second processor executes the first fault handler to transmit the at least one command to a command queue associated with the copy engine during the first page fault sequence.

12. The computing device of claim 11 , wherein the at least one command causes the copy engine to update a first page table associated with the first processor to include a first mapping associated with the first page fault.

13. The computing device of claim 8 , wherein the first processor includes a first streaming multiprocessor configured to execute a first thread associated with a first process, wherein the first thread causes the first page fault to be generated.

14. The computing device of claim 13 , wherein the first fault buffer entry includes an indication of an address space that is associated with the first page fault and with the first process.

15. A computing device for resolving page faults with a fault buffer, the computing device, comprising:
a first processor that comprises a copy engine;
a fault buffer configured to store a plurality of fault buffer entries, wherein a first fault buffer entry included in the plurality of fault buffer entries is associated with a first page fault generated by the first processor;
a second processor that executes a first fault handler to:
read the first fault buffer entry associated with the first page fault, and
trigger a first page fault sequence to resolve the first page fault, wherein the first page fault sequence includes executing at least one command by the copy engine included in the first processor,
wherein, in response to the first page fault, the second processor executes the first fault handler to transmit a plurality of commands to a command queue, and the copy engine executes the plurality of commands stored in the command queue to perform at least a portion of the first page fault sequence, and
wherein, when the copy engine executes a first command included in the plurality of commands stored in the command queue, the copy engine copies a page associated with the first page fault from the memory to a second memory of the first processor, and, when the copy engine executes a second command included in the plurality of commands stored in the command queue, the copy engine modifies an entry that is associated with the page and is included in a page table of the first processor; and

a second fault handler executed by the second processor, wherein the second fault handler is configured to resolve a second page fault generated by the second processor.

16. A computing device for resolving page faults with a fault buffer, the computing device, comprising:
a first processor that comprises a copy engine;
a fault buffer configured to store a plurality of fault buffer entries, wherein a first fault buffer entry included in the plurality of fault buffer entries is associated with a first page fault generated by the first processor;
a second processor that executes a first fault handler to:
read the first fault buffer entry associated with the first page fault,
trigger a first page fault sequence to resolve the first page fault, wherein the first page fault sequence includes executing at least one, command by the copy engine included in the first processor
determine a current ownership state for a memory page associated with the first page fault, and
in response, change the current ownership state of the page to a new ownership state,
wherein the current ownership state is second processor-owned, and the new ownership state is first processor-owned or second processor-shared,
wherein second processor-shared indicates that the page is stored in a memory of the second processor and a mapping to the page exists in a page table of the first processor that allows the f

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Buschardt Cameron
• Cheung Sherry
• Deming James Leroy
• Duncan Samuel H
• Dunning Lucien
• George Robert
• Gopalakrishnan Arvind
• Hairgrove Mark
• Jia Chenghuan
• Mashey John

Classifications

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/12

  Replacement control · CPC title