Robust transactional memory

Patent metadata

Field	Value
Publication number	US-10445238-B1
Application number	US-201815960927-A
Country	US
Kind code	B1
Filing date	Apr 24, 2018
Priority date	Apr 24, 2018
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Methods and apparatus are provided for executing a transaction in a data processing system, responsive to each memory access of the transaction, a transaction log is updated in a persistent memory. After execution of the transaction and when the transaction log is complete, the transaction log is marked as ‘pending’. When all values modified in the transaction have been written back to the persistent memory, the transaction log is marked as ‘free’. When, following a reboot, a transaction log is marked as ‘pending’, data stored in the transaction log is copied to the persistent memory at addresses indicated in the transaction log. After the copying is complete, the transaction log is marked as ‘free’. Cache values modified in the transaction may be written back to persistent memory when evicted, and values read in the transaction may be read from the cache rather than from the transaction log.

First claim

The invention claimed is:

1. A method of executing a transaction in a data processing system, where the transaction is performed by a first execution thread and comprises one or more instructions, the method comprising:
when, following a reboot of the data processing system, a first transaction log is indicated to be ‘pending’, where the first transaction log is stored in a persistent memory and is associated with a prior transaction:
copying data stored in the first transaction log to a data store at addresses indicated in the first transaction log, and
after the copying to the data store is complete, freeing the first transaction log;

responsive to a write instruction of the one or more instructions of the transaction:
writing a data value of the write instruction to an entry of a cache, where the entry is marked as being associated with the transaction, and
writing the data value of the write instruction to a second transaction log in the persistent memory;

after execution of the one or more instructions of the transaction, marking the second transaction log as ‘pending’; and
when all values in the transaction have been written back to the data store, marking the second transaction log as ‘free’.

2. The method of claim 1 , where:
marking the second transaction log as ‘free’ comprises resetting a first flag stored in the persistent memory; and
marking the second transaction log as ‘pending’ comprises setting a second flag stored in the persistent memory in response to an instruction to commit data modified in the transaction.

3. The method of claim 2 , further comprising, responsive to an instruction to begin the transaction:
assigning, as the second transaction log, a free transaction log in the persistent memory to the transaction; and
marking the second transaction log as ‘in use’ by setting the first flag stored in the persistent memory.

4. The method of claim 3 , further comprising providing the free transaction log by copying contents of a ‘pending’ transaction log to the persistent memory.

5. The method of claim 1 , where the entry in the cache is marked to associate it with the transaction and with the second transaction log.

6. The method of claim 5 , further comprising:
after execution of the one or more instructions of the transaction, unmarking the entry of the cache when the entry is written back to the data store to disassociate the entry of the cache with the transaction.

7. The method of claim 1 , further comprising detecting requests from a second execution thread to access data in marked entries of the cache.

8. The method of claim 1 , further comprising aborting the transaction when a marked entry is evicted from the cache.

9. The method of claim 1 , further comprising freeing the second transaction log when the transaction is aborted.

10. A method of executing a transaction in a data processing system, where the transaction is performed by a first execution thread and comprises one or more instructions, the method comprising:
responsive to each memory access of the transaction, updating a transaction log in a persistent memory;
after execution of the one or more instructions of the transaction and when the transaction log is complete, marking the transaction log as ‘pending’;
when all values modified in the transaction have been written back to the persistent memory, marking the transaction log as ‘free’; and
when, following a reboot of the data processing system, the transaction log is marked as ‘pending’:
copying data stored in the transaction log to the persistent memory at addresses indicated in the transaction log, and
after the copying from the transaction log to the persistent memory is complete, marking the transaction log as ‘free’.

11. A data processing system comprising:
a processor core configured to execute a transaction, where the transaction is performed by a first execution thread and comprises one or more instructions;
a cache accessible by the processing core, where a line of the cache includes a transaction identifier that is set when the line contains data accessed in the transaction;
a first persistent memory configured to store a transaction log;
a persistent storage location configured to store a status indicator that indicates when the transaction log is ‘pending’ and is to be processed following a reboot of the data processing system;
a memory controller;
a second persistent memory accessible by the processing core via the memory controller; and
reboot logic configured to update, following the reboot of the data processing system, the second persistent memory in accordance with the transaction log when the status indicator indicates the transaction log to be ‘pending’.

12. The data processing system of claim 11 , where the reboot logic is further configured to set the status indicator to indicate that the transaction log is ‘free’ when updating the second persistent memory in accordance with the transaction log is complete.

13. The data processing system of claim 11 , further comprising a coherence controller configured to detect requests from a second execution thread to access data in the transaction log of the first execution thread.

14. The data processing system of claim 13 , where the coherence controller implements a coherence protocol and where the line of the cache includes:
a line condition identifier that indicates when the line is in a ‘modified’ condition of the coherence protocol.

15. The data processing system of claim 11 , where the processor core is configured to abort the transaction when a second execution thread requests access to data in the transaction log of the first execution thread.

16. The data processing system of claim 11 , where, within the transaction, read operations to addresses in the transaction log are directed to the cache.

17. The data processing system of claim 11 , where the first persistent memory comprises a portion of the second persistent memory.

18. The data processing system of claim 11 , where the line of the cache includes:
an identifier that associates the transaction with the transaction log.

19. The data processing system of claim 11 , further comprising a counter, where the counter is incremented when a line is added to the cache during the transaction and is decremented when a line, associated with the transaction, is evicted from the cache and written back to persistent memory.

20. The data processing system of claim 19 , where the transaction log associated with the transaction is freed when the counter reaches zero, indicating that all cache lines associated with the transaction have been written back to the persistent memory.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Diestelhorst Stephan
• Wang Wei

Classifications

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title