Verify before program resume for memory devices

Patent metadata

Field	Value
Publication number	US-10445226-B2
Application number	US-201113814917-A
Country	US
Kind code	B2
Filing date	Aug 4, 2011
Priority date	Aug 10, 2010
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.

First claim

What is claimed is:

1. A method of programming a memory device including memory cells, the method comprising:
receiving at least one page program command, the page program command including a page address for addressing a page of the memory cells for a programming operation to program data in the addressed number of memory cells;
executing the at least one page program command by generating fractional program commands, queuing the fractional program commands, and for each fractional program command, generating a corresponding program pulse separate from the fractional program command, and iteratively carrying out at least one program/verify cycle upon execution of each fractional program command to incrementally program each of the addressed page of memory cells by incrementally increasing a threshold voltage of each memory cell, wherein a subsequent program pulse is not generated until a corresponding fractional program command is received;
selectively receiving a secondary command after initiating but before completing the programming operation, the selectively receiving occurring while pausing the programming operation, the secondary command inserted into the command queue between any of two adjacent selected fractional program commands;
storing programmed states of the page of memory cells for a most recent program/verify cycle in storage other than the page of memory cells while carrying out an operation corresponding to the secondary command; and
selectively resuming the programming operation by first retrieving the stored programmed states of the page of memory cells, verifying the page of memory cells, then carrying out at least one program/verify cycle on the page of memory cells.

2. The method of claim 1 wherein the page of memory cells are programmed simultaneously.

3. The method of claim 1 wherein:
selectively resuming the programming operation comprises receiving a program resume command, and in response to the program resume command, first verifying the memory cells, then carrying out at least one program/verify cycle.

4. The method of claim 1 wherein the at least one page program command comprises a partial program command to partially program the page of memory cells.

5. The method of claim 1 wherein the selectively receiving a secondary command comprises:
interrupting execution of the at least one program command with a non-program command.

6. The method of claim 1 , wherein each fractional program command initiates execution of a program/verify cycle.

7. The method of claim 1 wherein the fractional program commands comprise respective program and verify commands, and wherein the verifying of the memory cells is initiated by a verify command.

8. The method of claim 1 , wherein each fractional program command applies an incrementally increasing program voltage to the memory cells.

9. The method of claim 8 , wherein the storage other than the page of memory cells comprises a state register, and retrieving the stored program states comprises reading the stored program information from the state register, and resuming programming starting with the stored program information.

10. The method of claim 1 wherein executing the at least one page program command begins by first carrying out a verify operation.

11. The method of claim 1 wherein the at least one page program command comprises one of a first program command that when executed begins with a verify operation, or a second program command that when executed begins with a programming operation.

12. A method of programming a page of nonvolatile memory cells, the method comprising:
programming the number of memory cells by generating fractional program commands in response to a page program command, queuing the fractional program commands as independently executable commands in a command queue, for each fractional program command, generating a program pulse separate from the fractional program command, and applying a program voltage at an incremental level to the page of memory cells in response to each fractional program command, wherein a subsequent program pulse is not generated until a corresponding fractional program command is received;
verifying the page of memory cells;
iteratively repeating the applying and verifying on the page of memory cells by sequentially incrementally changing the program voltage toward a desired voltage level and verifying each incremental change in a threshold voltage of each memory cell;
pausing the programming by selectively receiving a secondary command after initiation but before completion of the programming on the page of memory cells to carry out a non-program operation, and inserting the secondary command between a selected two adjacent fractional program commands in the command queue; and
storing programmed states of the page of memory cells while carrying out the non-program operation.

13. The method of claim 12 and further comprising:
resuming programming of the page of memory cells, after pausing the programming, by first retrieving the stored programmed states of the page of memory cells, verifying the page of memory cells, then carrying out at least one more programming and verifying sequence on the page of memory cells.

14. The method of claim 13 wherein resuming programming of the memory cells by first verifying comprises executing a verify command before a program command.

15. A non-volatile memory device comprising:
an array of non-volatile memory cells;
command interface logic to receive at least one page program command, the page program command including a page address for addressing a page of the non-volatile memory cells, the at least one page program command to initiate respective program and verify operations for programming each cell by generating fractional program commands, queuing the fractional program commands, for each fractional program command, generating a program pulse separate from the fractional program command, and incrementally increasing a program voltage for each cell and verifying a cell voltage against an incrementally increasing threshold voltage value for each cell in response to each fractional program command, each programming and verifying operation responsive to each fractional program command and defining a program/verify cycle, wherein a subsequent program pulse is not generated until a corresponding fractional program command is received;
a program state register to store program information for a most-recent program/verify cycle;
the command interface logic to selectively receive a secondary command after initiation but before completion of the programming;
inserting the secondary command between any two adjacent selected fractional program commands; and
wherein before completion of the programming, the program state register stores the most-recent program information for the memory cells.

16. The non-volatile memory device of claim 15 wherein upon resuming programming, the program information for the memory cells is read from the program state register.

Assignees

• Shaeffer Ian
• Haukness Brent S
• Rambus Inc

Inventors

• Shaeffer Ian
• Haukness Brent S

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/344

  Arrangements for verifying correct erasure or for detecting overerased cells · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title