Memory system, memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-10445176-B2
Application number	US-201715810335-A
Country	US
Kind code	B2
Filing date	Nov 13, 2017
Priority date	Apr 10, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A memory system may include: a controller suitable for transmitting a command, an address and write data, and receiving read data, the command including a write command, a read command and a masked write command; and a memory device suitable for sequentially performing an internal read operation, an internal modification operation and an internal write operation in response to the masked write command while skipping the internal read operation when the masked write commands for the same address are consecutively inputted after the write command is inputted.

First claim

What is claimed is:

1. A memory system comprising:
a controller suitable for transmitting a command, an address and write data, and receiving read data, the command including a write command, a read command and a masked write command; and
a memory device suitable for sequentially performing an internal read operation, an internal modification operation and an internal write operation in response to the masked write command, wherein the internal read operation is skipped when the masked write commands for the same address are consecutively inputted after the write command is inputted.

2. The memory system of claim 1 , wherein the internal read operation comprises an operation of reading the read data and a read parity bit from memory cells corresponding to the address,
the internal modification operation comprises an operation of correcting an error of the read data using the read parity bit, and generating a write parity bit based on the error-corrected data and the write data, and
the internal write operation comprises an operation of writing the write data and the write parity bit to the memory cells corresponding to the address.

3. The memory system of claim 2 , wherein, when the internal read operation is skipped, the internal modification operation is performed by correcting an error in data previously stored in the memory device, using a parity bit previously stored in the memory device.

4. The memory system of claim 1 , wherein the memory device comprises:
a memory array region comprising memory cells;
a command control circuit suitable for sequentially generating an internal read command and an internal write command in response to the masked write command, and activating a read blocking signal when the masked write commands for the same address are consecutively inputted after the write command is inputted;
a read circuit disabled in response to the read blocking signal, and suitable for reading the read data and read parity bit from the memory array region corresponding to the address in response to the internal read command;
a write circuit suitable for writing the write data and write parity bit to the memory array region in response to the internal write command; and
an error correction circuit suitable for correcting an error of the read data using the read parity bit, or correcting an error of data stored in the write circuit using a parity bit stored in the write circuit, in response to the read blocking signal and the internal read command.

5. The memory system of claim 4 , wherein the error correction circuit generates the write parity bit based on the write data and the error-corrected data, in response to the internal write command.

6. The memory system of claim 4 , wherein, when the read blocking signal is activated, the error correction circuit corrects an error in the data stored in the write circuit using the parity bit stored in the write circuit.

7. The memory system of claim 4 , wherein the command control circuit comprises:
an internal command generator suitable for sequentially generating the internal read command and the internal write command when the masked write command is inputted; and
a masking controller suitable for activating the read blocking signal when the masked write commands for the same address are consecutively inputted after the write command is inputted.

8. The memory system of claim 7 , wherein the masking controller stores the address when the write command or the masked write command is inputted, and activates the read blocking signal by comparing the stored address to a currently inputted address according to the masked write command.

9. The memory system of claim 8 , wherein the masking controller resets the stored address when the read command is inputted.

10. A memory device comprising:
a normal cell region and parity region;
an internal command generator suitable for sequentially generating an internal read command and an internal write command when a masked write command is inputted;
a masking controller suitable for activating a read blocking signal when the masked write commands for a same address are consecutively inputted after a write command is inputted;
a read circuit disabled in response to the read blocking signal, and suitable for reading read data and a read parity bit from the normal cell region and the parity region, respectively, in response to the internal read command;
a write circuit suitable for writing masked write data and a write parity bit to the normal cell region and the parity region, respectively, and storing the masked write data and the write parity bit therein, in response to the internal write command; and
an error corrector suitable for correcting an error in the read data using the read parity bit, or correcting an error in the masked write data stored in the write circuit using the write parity bit stored in the write circuit, in response to the read blocking signal and the internal read command.

11. The memory device of claim 10 , further comprising:
a data input circuit suitable for generating the masked write data containing one or more masked bits by masking write data according to a data mask signal; and
a parity generator suitable for generating the write parity bit based on the masked write data and the error-corrected data, in response to the internal write command.

12. The memory device of claim 10 , wherein the masking controller comprises:
a first latch unit suitable for storing the address when the write command or the masked write command is inputted;
a second latch unit suitable for storing an output of the first latch unit according to the masked write command;
a blocking determination unit suitable for generating a comparison enable signal when the masked write command is inputted after the write command or the masked write command is inputted; and
an address comparison unit suitable for comparing the address with an output of the second latch unit according to the comparison enable signal, and activating the read blocking signal according to a comparison result.

13. The memory device of claim 12 , wherein the blocking determination unit generates a reset signal for resetting the first and second latch units when a read command is inputted.

14. An operating method for a memory device, comprising:
receiving a masked write command and an address;
sequentially generating an internal read command and an internal write command in response to the masked write command;
activating a read blocking signal when the masked write commands for the same address are consecutively inputted after a write command is inputted;
correcting an error in data previously stored in the memory device using a parity bit previously stored in the memory device in response to the internal read command, when the read blocking signal is activated;
receiving masked write data;
generating a write parity bit based on the masked write data and the error-corrected data, in response to the internal write command; and
writing the masked write data and the write parity bit to memory cells corresponding to the address.

15. The operating method of claim 14 , wherein the writing of the masked write data and the write parity bit to the memory cells is performed by a write circuit, and the write circuit stores the masked write data and the write parity bit as the previously stored data and the previously stored parity bit, respectively.

16. The operating method of claim 14 , further comprising:
correcting an error of read data from the memory cells corresponding to the address using a read parity data

Assignees

• Sk Hynix Inc

Inventors

• Lee Jeong-Jun

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C7/1009

  Data masking during input/output · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title