Sensing chip, sensing chip manufacturing method, sensing kit, measuring method and measuring device
US-2024319093-A1 · Sep 26, 2024 · US
US10444151B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10444151-B2 |
| Application number | US-201515570364-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 29, 2015 |
| Priority date | Jul 29, 2015 |
| Publication date | Oct 15, 2019 |
| Grant date | Oct 15, 2019 |
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Provided in one example is an analyte detection apparatus that includes surface enhanced luminescence (SEL) structure. A dielectric layer underlies the SEL structure. An electric field generating base underlies the dielectric layer. The electric field generating base is to apply an electric field about the SEL structures to attract charged ions to the SEL structures.
Opening claim text (preview).
What is claimed is: 1. An analyte detection apparatus comprising: a surface enhanced luminescence (SEL) structure; a dielectric layer underlying the SEL structure; and an electric field generating base underlying the dielectric layer, the electric field generating base to apply an electric field about the SEL structure to attract charged ions to the SEL structure, wherein the electric field generating base comprises an integrated transistor. 2. The analyte detection package of claim 1 further comprising a metal floor from which the SEL structure extends, wherein the dielectric layer underlies the metal floor. 3. The analyte detection apparatus of claim 2 further comprising a housing above the metal floor and over the SEL structure, the housing supporting a counter electrode to facilitate the generation of the electric field. 4. The analyte detection apparatus of claim 2 , wherein the housing forms a fluid chamber and wherein the counter electrode is supported within the fluid chamber. 5. The analyte detection apparatus of claim 1 , wherein the electric field generating base comprises a floating gate. 6. The analyte detection apparatus of claim 5 further comprising a selection transistor to selectively control charging of the floating gate. 7. The analyte detection apparatus of claim 1 , wherein the electric field generating base comprises an erasable programmable read-only memory (EPROM) chip. 8. The analyte detection apparatus of claim 1 , wherein the electric field generating base comprises: a substrate; a source electrode supported by the substrate; a drain electrode supported by the substrate; a channel material between the source electrode in the drain electrode; and a floating gate spaced opposite the channel material between the source electrode and the drain electrode, wherein the dielectric layer is between the floating gate and the SEL structure. 9. The analyte detection apparatus of claim 1 , wherein the SEL structure is part of a group of SEL structures, the SEL structure comprising a flexible columnar support. 10. The analyte detection apparatus of claim 9 , wherein the flexible columnar support comprises a metal. 11. The analyte detection apparatus of claim 9 , wherein each of the SEL structures is self-actuating such that the columnar structures bend towards one another in response to micro capillary forces to self-organize. 12. The apparatus of claim 1 further comprising: a housing forming a fluid chamber about the SEL structure and over the electric field generating base, the housing comprising fill openings; and a seal temporarily closing the fill openings, the seal being alterable to open the fill openings. 13. An apparatus comprising: an erasable programmable read-only memory (EPROM) device providing an electric field generating base; a dielectric layer supported by the EPROM device; and a dielectric surface enhanced luminescence (SEL) structure extending above the dielectric layer. 14. The apparatus of claim 13 further comprising a metal floor supported by the dielectric layer. 15. The apparatus of claim 14 further comprising: a housing cooperating with the metal floor to form a chamber about the SEL structure; and a counter electrode supported by the housing. 16. The apparatus of claim 15 , wherein the housing comprises a metal layer forming the counter electrode. 17. A method comprising: forming a surface enhanced luminescence (SEL) structure above an upper dielectric layer of an electric field generating base. 18. The method of claim 16 further comprising storing an electrical charge on the electric field generating base. 19. The method of claim 16 further comprising forming a metal floor above the dielectric layer and housing above the metal floor, the housing cooperating with the metal floor to form a chamber and supporting a counter electrode spaced from the metal floor. 20. The method of claim 16 , wherein the electric field generating base comprises a floating gate transistor.
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