Method and device for signal converting

Patent metadata

Field	Value
Publication number	US-10439629-B2
Application number	US-201816164015-A
Country	US
Kind code	B2
Filing date	Oct 18, 2018
Priority date	Oct 24, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

In accordance with an embodiment, a method includes adding a dither signal to a first signal to generate a second signal, subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal, performing a first sigma delta conversion of the second signal to a digital fourth signal, performing a second signal delta conversion of the third signal to a digital fifth signal, combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.

First claim

What is claimed is:

1. A method comprising:
adding a dither signal to a first signal to generate a second signal;
subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal;
performing a first sigma delta conversion of the second signal to a digital fourth signal;
performing a second signal delta conversion of the third signal to a digital fifth signal; and
combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.

2. The method as claimed in claim 1 , wherein at least one of the digital fourth signal, the digital fifth signal, or the digital sixth signal is a 1 bit stream.

3. The method as claimed in claim 1 , wherein the performing the first sigma delta conversion and the performing the second signal delta conversion proceed correspondingly.

4. The method as claimed in claim 1 , wherein the digital fourth signal and the digital fifth signal have a first sampling frequency and the digital sixth signal has a second sampling frequency, wherein the first sampling frequency is lower than the second sampling frequency.

5. The method as claimed in claim 4 , wherein the second sampling frequency is an integral multiple of double the first sampling frequency.

6. The method as claimed in claim 1 , wherein the dither signal is a periodic signal.

7. The method as claimed in claim 6 , wherein a dither frequency of the dither signal is less than a lower useful frequency of the first signal.

8. The method as claimed in claim 1 , wherein the performing the first sigma delta conversion and the performing the second signal delta conversion comprise
either converting an analog signal into a digital signal; or
converting a digital signal from a first bit width to a second bit width.

9. The method as claimed in claim 1 , wherein the combining comprises alternately combining the digital fourth signal and the digital fifth signal.

10. A device comprising:
a first sigma delta converter having a first conversion input and a first conversion output;
a second sigma delta converter having a second conversion input and a second conversion output;
wherein the first conversion input and the second conversion input are coupled to an input signal line;
a dither generator, which is additively coupled to the first conversion input and is subtractively coupled to the second conversion input; and
a combination circuit, which is coupled to the first conversion output and the second conversion output and to an output signal line.

11. A device comprising:
an adder for adding a dither signal to a first signal in order to generate a second signal;
a subtractor for subtracting the dither signal from the first signal or for subtracting the first signal from the dither signal in order to generate a third signal;
a first sigma delta converter for converting the second signal to a digital fourth signal;
a second sigma delta converter for converting the third signal to a digital fifth signal; and
a combination circuit for combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.

12. The device as claimed in claim 11 , wherein the first sigma delta converter and the second sigma delta converter correspond to one another.

13. The device as claimed in claim 11 , wherein the first sigma delta converter and the second sigma delta converter are configured to convert either an analog signal into a digital signal or a digital signal from a first bit width to a second bit width.

14. The device as claimed in claim 11 , wherein at least one of the digital fourth signal, the digital fifth signal, or the digital sixth signal is a 1 bit stream.

15. The device as claimed in claim 11 , wherein the digital fourth signal and the digital fifth signal have a first sampling frequency and the digital sixth signal has a second sampling frequency, wherein the first sampling frequency is lower than the second sampling frequency.

16. The device as claimed in claim 15 , wherein the second sampling frequency is an integral multiple of double the first sampling frequency.

17. The device as claimed in claim 11 , wherein the dither signal is a periodic signal.

18. The device as claimed in claim 17 , wherein a dither frequency of the dither signal is less than a lower useful frequency of the first signal.

19. The device as claimed in claim 11 , wherein the combination circuit is configured to carry out a process of alternately combining the digital fourth signal and the digital fifth signal.

20. The device as claimed in claim 11 , wherein the first sigma delta converter and the second sigma delta converter each comprise a digital modulator.

21. A microphone comprising:
a sound transducer configured to convert acoustic oscillations into electrical signals and to provide them as a microphone signal; and
a device coupled to an output of the sound transducer, the device comprising
an adder for adding a dither signal to the microphone signal in order to generate a second signal,
a subtractor for subtracting the dither signal from the microphone signal or for subtracting the microphone signal from the dither signal in order to generate a third signal,
a first sigma delta converter for converting the second signal to a digital fourth signal,
a second sigma delta converter for converting the third signal to a digital fifth signal, and
a combination circuit for combining the digital fourth signal and the digital fifth signal to form a digital output signal of the device.

Assignees

• Infineon Technologies Ag

Inventors

• Straeussnigg Dietmar

Classifications

• H03M1/0639 Primary

  using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M1/201) · CPC title

• H04R1/222

  for microphones (H04R1/24, H04R1/26 take precedence) · CPC title

• H03M1/0836 Primary

  of phase error, e.g. jitter · CPC title

• H03M1/08

  of noise {(H03M1/0617 takes precedence)} · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title