Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10438927-B2
Application number	US-201815986212-A
Country	US
Kind code	B2
Filing date	May 22, 2018
Priority date	Dec 15, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a core member having a first through-hole and including first and second wiring layers disposed on different levels;
a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface and disposed in the first through-hole;
a second semiconductor chip having a second active surface having second connection pads disposed thereon and a second inactive surface opposing the second active surface and disposed on the first semiconductor chip in the first through-hole so that the second inactive surface faces the first inactive surface;
conductive wires disposed on the core member and the second active surface and electrically connecting the second connection pads and the second wiring layer to each other;
an encapsulant covering at least portions of the core member, the first semiconductor chip, and the second semiconductor chip, the encapsulant filling at least portions of the first through-hole and embedding the conductive wires;
a connection member disposed on the core member and the first active surface and electrically connecting the first connection pads and the first wiring layer to each other;
a passivation layer disposed on a surface of the connection member opposing another surface of the connection member on which the core member is disposed and having openings exposing at least portions of the connection member; and
electrical connection structures disposed in the openings of the passivation layer and electrically connected to the exposed portions of the connection member,
wherein the first and second semiconductor chips are spaced apart from the core member by the encapsulant.

2. The fan-out semiconductor package of claim 1 , wherein the connection member includes an insulating layer disposed on the core member and the first active surface and covering at least portions of the first wiring layer and the first connection pads, a redistribution layer disposed on the insulating layer, and vias penetrating through the insulating layer and electrically connecting the redistribution layer to the first wiring layer and the first connection pads.

3. The fan-out semiconductor package of claim 2 , wherein the insulating layer includes a photoimagable dielectric (PID) resin.

4. The fan-out semiconductor package of claim 1 , wherein the connection member includes an insulating layer disposed on the core member and the first active surface and having openings exposing at least portions of each of the first wiring layer and the first connection pads and flexible conductors disposed on the insulating layer, bent in the openings of the insulating layer, and electrically connecting the first wiring layer and the first connection pads to each other.

5. The fan-out semiconductor package of claim 4 , wherein the flexible conductor is in direct contact with the first wiring layer and the first connection pad.

6. The fan-out semiconductor package of claim 1 , wherein edges of the first and second semiconductor chips are aligned with each other in a stacking direction of the first and second semiconductor chips.

7. The fan-out semiconductor package of claim 1 , wherein the number of first connection pads is greater than that of second connection pads.

8. The fan-out semiconductor package of claim 1 , wherein the core member includes a first insulating layer, the first wiring layer embedded in the first insulating layer so that one surface thereof is exposed, a third wiring layer disposed on the other surface of the first insulating layer opposing the one surface of the first insulating layer in which the first wiring layer is embedded, a second insulating layer disposed on the first insulating layer and covering the third wiring layer, and the second wiring layer disposed on the second insulating layer, and
the first to third wiring layers are electrically connected to each other.

9. The fan-out semiconductor package of claim 8 , wherein the one surface of the first insulating layer and one surface of the first wiring layer have a step therebetween.

10. The fan-out semiconductor package of claim 1 , wherein the core member includes a first insulating layer, the first wiring layer disposed on one surface of the first insulating layer, and the second wiring layer disposed on the other surface of the first insulating layer, and
the first and second wiring layers are electrically connected to each other.

11. The fan-out semiconductor package of claim 1 , wherein the core member includes a first insulating layer, a third wiring layer disposed on one surface of the first insulating layer, a fourth wiring layer disposed on the other surface of the first insulating layer, a second insulating layer disposed on the one surface of the first insulating layer and covering the third wiring layer, the first wiring layer disposed on the second insulating layer, a third insulating layer disposed on the other surface of the first insulating layer and covering the fourth wiring layer, and the second wiring layer disposed on the third insulating layer, and
the first to fourth wiring layers are electrically connected to each other.

12. The fan-out semiconductor package of claim 11 , wherein the first insulating layer has a thickness greater than that of each of the second and third insulating layers.

13. The fan-out semiconductor package of claim 1 , wherein the core member further has a second through-hole spaced apart from the first through-hole,
the fan-out semiconductor package further comprises: a third semiconductor chip having a third active surface having third connection pads disposed thereon and a third inactive surface opposing the third active surface is disposed in the second through-hole, and a fourth semiconductor chip having a fourth active surface having fourth connection pads disposed thereon and a fourth inactive surface opposing the fourth active surface is disposed on the third semiconductor chip in the second through-hole so that the fourth inactive surface faces the third inactive surface,
the conductive wires electrically connect the fourth connection pads and the second wiring layer to each other, and
the connection member electrically connects the third connection pads and the first wiring layer to each other.

14. The fan-out semiconductor package of claim 13 , wherein the first and second semiconductor chips stacked in the first through-hole and the third and fourth semiconductor chips stacked in the second through-hole are disposed side-by-side, and are electrically connected to each other through the connection member.

15. A fan-out semiconductor package comprising:
a core member having a first through-hole and including first and second wiring layers disposed on different levels;
a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface and disposed in the first through-hole;
a second semiconductor chip having a second active surface having second connection pads disposed thereon and a second inactive surface opposing the second active surface and disposed on the first semiconductor chip in the first through-hole so that the second inactive surface faces the first inactive surface;
conductive wires disposed on the core member and the second active surface and electrically connecting the second connection pads and the second wiring layer to each other;
an encapsulant covering at least portions of the core member, the first semiconductor chip,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Ha Yong
• Choi Jae Min
• Lee Jae Kul
• Kim Dong Jin
• Woo Sung Taek
• Shim Ji Hye
• Choi Woon Ha
• Cho Han Sang

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title