Wiring board and semiconductor device

Patent metadata

Field	Value
Publication number	US-10438883-B2
Application number	US-201715819310-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Dec 26, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A wiring board includes an insulator layer having a top surface, and a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer. The pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density. At least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region.

First claim

What is claimed is:

1. A wiring board comprising:
an insulator layer having a top surface;
a wiring layer covered by the insulator layer; and
a plurality of pads directly formed on the top surface of the insulator layer in a pad arrangement region on the top surface of the insulator layer,
wherein the pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density and electrically connect to the wiring layer, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density and electrically connect to the wiring layer,
wherein at least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region, and
wherein the at least one dummy pad does not contribute to an electrical connection.

2. The wiring board according to claim 1 , wherein the at least one dummy pad is arranged outside the second region of the pad arrangement region, juxtaposed to the at least one of the second plurality of pads located at an outermost peripheral part of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer.

3. The wiring board according to claim 1 , further comprising:
a plated layer formed on a surface of each of the plurality of pads,
wherein the plated layer includes nickel.

4. The wiring board according to claim 1 , wherein a plurality of dummy pads are arranged juxtaposed to the second plurality of pads of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer, and at least a part of the second plurality of pads are arranged in a staggered pattern with the plurality of dummy pads.

5. The wiring board according to claim 2 , wherein a distance between the at least one dummy pad and the one of the second plurality of pads located at an outermost peripheral part of the second region and nearest to the at least one dummy pad is shorter than a distance between two mutually adjacent second pads inside the second region.

6. The wiring board according to claim 1 , wherein a plurality of dummy pads are arranged juxtaposed to the second plurality of pads of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer, and the plurality of dummy pads are arranged at a pitch shorter than a pitch of mutually adjacent second pads inside the second region.

7. The wiring board according to claim 1 , wherein a plurality of dummy pads are arranged juxtaposed to the second plurality of pads of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer, and the plurality of dummy pads are located in at least one of a region outside the second region, a region at an outermost peripheral part inside the second region, and a region at an inner side of the outermost peripheral part inside the second region.

8. The wiring board according to claim 7 , wherein the plurality of dummy pads are located in both the region at the outermost peripheral part inside the second region so that at least one of the plurality of dummy pads is arranged between two of the second plurality of pads in the region at the outermost peripheral part inside the second region, and the region at the inner side of the outermost peripheral part inside the second region so that at least one of the plurality of dummy pads is arranged between two of the second plurality of pads in the region at the inner side of the outermost peripheral part inside the second region.

9. The wiring board according to claim 1 , wherein the at least one dummy pad has a pattern that is elongated along one side of the second region, juxtaposed to the second plurality of pads located at an outermost peripheral part along the one side of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer.

10. The wiring board according to claim 1 , wherein a plurality of columns of dummy pads are arranged outside the second region, juxtaposed to the second plurality of pads located at an outermost peripheral part of the second region, in the plan view viewed in a direction perpendicular to the top surface of the insulator layer.

11. A semiconductor device comprising:
a wiring board including
an insulator layer having a top surface, and
a plurality of pads arranged in a pad arrangement region on the top surface of the insulator layer,
wherein the pad arrangement region includes a first region in which a first plurality of pads among the plurality of pads are arranged at a first density, and a second region in which a second plurality of pads among the plurality of pads are arranged at a second density lower than the first density, and
wherein at least one dummy pad is arranged juxtaposed to at least one of the second plurality of pads in the second region of the pad arrangement region;

a semiconductor chip electrically connected to the plurality of pads of the wiring board; and
a resin provided between the wiring board and the semiconductor chip,
wherein the resin covers the at least one dummy pad, and
wherein the at least one dummy pad is electrically insulated from the semiconductor chip.

12. The semiconductor device according to claim 11 , wherein the at least one dummy pad of the wiring board is arranged outside the second region of the pad arrangement region, juxtaposed to at least one of the second plurality of pads located at an outermost peripheral part of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer.

13. The semiconductor device according to claim 11 , wherein the wiring board further includes
a plated layer, including nickel, and formed on a surface of each of the plurality of pads.

14. The semiconductor device according to claim 11 , wherein the wiring board includes a plurality of dummy pads arranged juxtaposed to the second plurality of pads of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer, and at least a part of the second plurality of pads are arranged in a staggered pattern with the plurality of dummy pads.

15. The semiconductor device according to claim 12 , wherein a distance between the at least one dummy pad and one of the second plurality of pads located at an outermost peripheral part of the second region and nearest to the at least one dummy pad is shorter than a distance between two mutually adjacent second pads inside the second region.

16. The semiconductor device as claimed in claim 11 , wherein the wiring board includes a plurality of dummy pads arranged juxtaposed to the second plurality of pads of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer, and the plurality of dummy pads are arranged at a pitch shorter than a pitch of mutually adjacent second pads inside the second region.

17. The semiconductor device according to claim 11 , wherein the wiring board includes a plurality of dummy pads arranged juxtaposed to the plurality of second pads of the second region, in a plan view viewed in a direction perpendicular to the top surface of the insulator layer, and the plurality of dummy pads are located in at least one of a region outside the second region, a region at an outermost peripheral part inside the second region, and a region at an inner side of the out

Assignees

• Shinko Electric Ind Co

Inventors

• Imafuji Kei

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/931

  Shapes of bond pads · CPC title