Multilayer electronic component

US10438747B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10438747-B2
Application numberUS-201815911244-A
CountryUS
Kind codeB2
Filing dateMar 5, 2018
Priority dateMar 21, 2017
Publication dateOct 8, 2019
Grant dateOct 8, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer electronic component includes first, second, and third ceramic layers, first and second inner electrodes, and a via-electrode. The first, second and third ceramic layers are sequentially stacked on each other. The first inner electrode is sandwiched between the first and second ceramic layers. The second inner electrode is sandwiched between the second and third ceramic layers. The via-electrode electrically connects the first and second inner electrodes. A projection is integrally provided with the via-electrode. The projection projects from the via-electrode towards an outer peripheral direction and is inserted into the second ceramic layer in a layered arrangement.

First claim

Opening claim text (preview).

What is claimed is: 1. A multilayer electronic component, comprising: first, second, and third ceramic layers sequentially stacked on each other; a first inner electrode sandwiched between the first and second ceramic layers; a second inner electrode sandwiched between the second and third ceramic layers; and a via-electrode that electrically connects the first and second inner electrodes; wherein a projection is integrally provided with the via-electrode, the projection projecting from the via-electrode towards an outer peripheral direction and extending into the second ceramic layer in a layered arrangement; and the projection has a wedge or substantial wedge shape such that a thickness of the projection decreases from a base portion to a leading portion of the projection. 2. The multilayer electronic component according to claim 1 , wherein the projection is curved from a base portion to a leading portion of the projection. 3. The multilayer electronic component according to claim 1 , wherein a ratio of a common material to a metal material included in the via-electrode is higher than a ratio of the common material to a metal material included in the first and second inner electrodes, the common material being included in common with the first, second, and third ceramic layers. 4. The multilayer electronic component according to claim 1 , further comprising an outer electrode provided on an outer surface of the multilayer electronic component and connected to the via-electrode. 5. The multilayer electronic component according to claim 1 , wherein the projection has a flat or a substantially flat shape. 6. The multilayer electronic component according to claim 1 , wherein the projection is defined by a flange that extends around an entire or substantially entire periphery of the via-electrode. 7. The multilayer electronic component according to claim 1 , wherein the projection is sandwiched between the first and second ceramic layers. 8. The multilayer electronic component according to claim 1 , wherein the projection extends perpendicularly or substantially perpendicularly to an axial direction of the via-electrode. 9. The multilayer electronic component according to claim 1 , wherein the first and second inner electrodes are solid plane electrodes. 10. The multilayer electronic component according to claim 1 , wherein the multilayer electronic component is a capacitor. 11. The multilayer electronic component according to claim 1 , wherein the first and second inner electrodes and the via-electrode include at least one of Ni, Ag, Pd, Au, or Cu or an alloy including at least two of Ni, Ag, Pd, Au, or Cu as a primary component. 12. A multilayer electronic component comprising: first, second, and third ceramic layers sequentially stacked on each other; a first inner electrode sandwiched between the first and second ceramic layers; a second inner electrode sandwiched between the second and third ceramic layers; and a via-electrode that electrically connects the first and second inner electrodes; wherein a projection is integrally provided with the via-electrode, the projection projecting from the via-electrode towards an outer peripheral direction and extending into the second ceramic layer in a layered arrangement; and a projecting length of the projection is greater than a thickness of a base portion of the projection. 13. A multilayer electronic component comprising: first, second, and third ceramic layers sequentially stacked on each other; a first inner electrode sandwiched between the first and second ceramic layers; a second inner electrode sandwiched between the second and third ceramic layers; and a via-electrode that electrically connects the first and second inner electrodes; wherein a projection is integrally provided with the via-electrode, the projection projecting from the via-electrode towards an outer peripheral direction and extending into the second ceramic layer in a layered arrangement; and the projection projects obliquely with respect to planes of the first and second inner electrodes.

Assignees

Inventors

Classifications

  • electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • Form of non-self-supporting electrodes · CPC title

  • Selection of materials · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

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Frequently asked questions

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What does patent US10438747B2 cover?
A multilayer electronic component includes first, second, and third ceramic layers, first and second inner electrodes, and a via-electrode. The first, second and third ceramic layers are sequentially stacked on each other. The first inner electrode is sandwiched between the first and second ceramic layers. The second inner electrode is sandwiched between the second and third ceramic layers. The…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 08 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).