Apparatus for low power write and read operations for resistive memory

Patent metadata

Field	Value
Publication number	US-10438640-B2
Application number	US-201816052552-A
Country	US
Kind code	B2
Filing date	Aug 1, 2018
Priority date	Jun 28, 2013
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

First claim

We claim:

1. An apparatus comprising:
a resistive memory cell coupled to a bit line and a select line;
a first pass-gate coupled to the bit line;
a second pass-gate coupled to the select line;
a first write driver to drive an input data to the first pass-gate, the first write driver having a first drive skew; and
a second write driver to drive an inverse of the input data to the second pass-gate, the second write driver having a second drive skew, wherein the first drive skew is different than the second drive skew.

2. The apparatus of claim 1 comprises logic to adjust first and second drive skews of the first and second write drivers.

3. The apparatus of claim 2 , wherein the logic is to dynamically adjust first and second drive skews of the first and second write drivers according to the input data.

4. The apparatus of claim 1 further comprises: a multiplexer operable by the input data, wherein the multiplexer is to provide a control signal to the first and second pass-gates according to logic level of the input data.

5. The apparatus of claim 4 , wherein the multiplexer is to receive at least two inputs of different pulse widths.

6. The apparatus of claim 4 further comprises logic to adjust pulse widths of the at least two inputs.

7. The apparatus of claim 6 , wherein the at least two inputs are first and second write enable pulses, wherein the first write enable pulse is to control duration of writing a logical high to the resistive memory, and wherein the second write enable pulse is to control duration of writing a logical low to the resistive memory.

8. The apparatus of claim 1 , wherein the resistive memory is at least one of: STT-MRAM; ReRAM; PCM; or CBRAM.

9. The apparatus of claim 1 , wherein the resistive memory is an STT-MRAM bit-cell which comprises:
a select transistor controllable by a word line; and
a magnetic tunnel junction (MTJ) device coupled in series with the select transistor.

10. A system comprising:
a processor;
a wireless interface to allow the processor to communicate with another device;
a memory coupled to the processor, the memory comprising:
a resistive memory cell coupled to a bit line and a select line;

a first pass-gate coupled to the bit line;
a second pass-gate coupled to the select line;
a first write driver to drive an input data to the first pass-gate, the first write driver having a first drive skew; and
a second write driver to drive an inverse of the input data to the second pass-gate, the second write driver having a second drive skew, wherein the first drive skew is different than the second drive skew; and

a display unit to display content processed by the processor.

11. The system of claim 10 , wherein the display unit is a touch screen.

Assignees

• Intel Corp

Inventors

• Wei Liqiong
• Hamzaoglu Fatih
• Wang Yih
• August Nathaniel J
• Lin Blake C
• Dray Cyrille

Classifications

• G11C13/003

  Cell access · CPC title

• G11C2213/74

  Array wherein each memory cell has more than one access device · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title