Circuit for removing residual image after power-off, method for driving same, and display apparatus

Patent metadata

Field	Value
Publication number	US-10438546-B2
Application number	US-201715552286-A
Country	US
Kind code	B2
Filing date	Feb 6, 2017
Priority date	Jun 17, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

The embodiments of the present disclosure provide a circuit for removing residual image after power-off, a method for driving the circuit, and a display apparatus. The circuit comprises a comparator, a control circuit and an output circuit. The comparator is configured to output a high level voltage when a voltage at its non-inverting terminal is higher than a voltage at its inverting terminal, or output a low level voltage when the input voltage at its non-inverting terminal is lower than or equal to the input voltage at its inverting terminal. The control circuit is configured to align a voltage at the control node with a voltage at the second level terminal when the comparator outputs the high level voltage, and align the voltage at the control node with a voltage at the third level terminal when the comparator outputs the low level voltage. The output circuit is configured to output a voltage of the fourth level terminal at the signal output terminal when the voltage at the control node is the voltage at the third level terminal, and output a voltage of the fifth level terminal at the signal output terminal when the voltage at the control node is the voltage at the second level terminal.

First claim

What is claimed is:

1. A circuit for removing residual image after power-off, comprising:
a comparator having an inverting terminal connected to a first level terminal and a non-inverting terminal connected to a control voltage input terminal for receiving a voltage of a main power supply of a display apparatus, and configured to output a high level voltage at its output terminal when an input voltage at the non-inverting terminal is higher than an input voltage at the inverting terminal, or output a low level voltage at its output terminal when the input voltage at the non-inverting terminal is lower than or equal to the input voltage at the inverting terminal;
a control circuit connected to a second level terminal, a third level terminal, a control node and the output terminal of the comparator, and configured to align a voltage at the control node with a voltage at the second level terminal when the output terminal of the comparator outputs the high level voltage, and align the voltage at the control node with a voltage at the third level terminal when the output terminal of the comparator outputs the low level voltage; and
an output circuit connected to a fourth level terminal, a fifth level terminal, a signal output terminal for outputting a control signal of a gate driving circuit of the display apparatus, and the control node, and configured to output a voltage of the fourth level terminal at the signal output terminal when the voltage at the control node is the voltage at the third level terminal, and output a voltage of the fifth level terminal at the signal output terminal when the voltage at the control node is the voltage at the second level terminal,
wherein the voltage of the fourth level terminal is the high level voltage and the voltage of the fifth level terminal is the low level voltage, and wherein each of the first level terminal, the second level terminal, the third level terminal, the fourth level terminal and the fifth level terminal provides a stable voltage that is independent of the voltage of the main power supply of the display apparatus.

2. The circuit of claim 1 , further comprising: a voltage divider circuit connected to an input voltage terminal, the second level terminal and the control voltage input terminal, and configured to adjust the voltage at the control voltage input terminal.

3. The circuit of claim 2 , wherein the voltage divider circuit comprises a first resistor and a second resistor, wherein:
the first resistor has its first terminal connected to the input voltage terminal and its second terminal connected to the control voltage input terminal, and
the second resistor has its first terminal connected to the control voltage input terminal and its second terminal connected to the second level terminal.

4. The circuit of claim 2 , wherein the output circuit comprises a second transistor and a third transistor, wherein:
the second transistor has its first terminal connected to the fourth level terminal, its second terminal connected to the signal output terminal, and its gate connected to the control node,
the third transistor has its first terminal connected to the signal output terminal, its second terminal connected to the fifth level terminal, and its gate connected to the control node, and
the second transistor is an N-type transistor and the third transistor is a P-type transistor.

5. The circuit of claim 2 , wherein the output circuit comprises an inverter circuit, a fourth transistor and a fifth transistor, wherein:
the inverter circuit has its input terminal connected to the control node and its output terminal connected to the gate of the fourth transistor, and is configured to output a voltage at its output terminal that has an opposite phase to a voltage inputted at its input terminal,
the fourth transistor has its first terminal connected to the fourth level terminal, its second terminal connected to the signal output terminal, and its gate connected to the output terminal of the inverter circuit,
the fifth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the fifth level terminal, and its gate connected to the control node, and
each of the fourth and fifth transistors is a P-type transistor.

6. The circuit of claim 5 , wherein the inverter circuit comprises an inverter or an OR gate.

7. The circuit of claim 2 , wherein the output circuit comprises an inverter circuit, a fourth transistor and a fifth transistor, wherein:
the inverter circuit has its input terminal connected to the control node and its output terminal connected to the gate of the fifth transistor, and is configured to output a voltage at its output terminal that has an opposite phase to a voltage inputted at its input terminal,
the fourth transistor has its first terminal connected to the fourth level terminal, its second terminal connected to the signal output terminal, and its gate connected to the control node,
the fifth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the fifth level terminal, and its gate connected to the output terminal of the inverter circuit, and
each of the fourth and fifth transistors is an N-type transistor.

8. The circuit of claim 7 , wherein the inverter circuit comprises an inverter or an OR gate.

9. The circuit of claim 1 , further comprising: a filter circuit connected to the control node and the second level terminal, and configured to filter the voltage at the control node.

10. The circuit of claim 9 , wherein the filter circuit comprises at least one capacitor having its first terminal connected to the control node and its second terminal connected to the second level terminal.

11. The circuit of claim 1 , wherein the control circuit comprises: a first transistor having its first terminal connected to the control node and the third level terminal, its second terminal connected to the second level terminal, and its gate connected to the output terminal of the comparator.

12. The circuit of claim 1 , wherein the output circuit comprises a second transistor and a third transistor, wherein:
the second transistor has its first terminal connected to the fourth level terminal, its second terminal connected to the signal output terminal, and its gate connected to the control node,
the third transistor has its first terminal connected to the signal output terminal, its second terminal connected to the fifth level terminal, and its gate connected to the control node, and
the second transistor is an N-type transistor and the third transistor is a P-type transistor.

13. The circuit of claim 1 , wherein the output circuit comprises an inverter circuit, a fourth transistor and a fifth transistor, wherein:
the inverter circuit has its input terminal connected to the control node and its output terminal connected to the gate of the fourth transistor, and is configured to output a voltage at its output terminal that has an opposite phase to a voltage inputted at its input terminal,
the fourth transistor has its first terminal connected to the fourth level terminal its second terminal connected to the signal output terminal, and its gate connected to the output terminal of the inverter circuit,
the fifth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the fifth level terminal, and its gate connected to the control node, and
each of the fourth and fifth transistors is a P-type transistor.

14. The circuit of claim 13 , wherein the inverter circuit comprises an inverter or an OR gate.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Yang Yuting
• Hu Lingxiao
• Ye Chun

Classifications

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2330/027

  Arrangements or methods related to powering off a display · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/36 Primary

  using liquid crystals · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title