Computer system and display interface circuit and display interface method thereof

Patent metadata

Field	Value
Publication number	US-10438530-B2
Application number	US-201715857656-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Nov 30, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A display interface circuit includes a first transistor and a second transistor electrically connecting in series between a first motherboard power and a display power. A first body diode of the first transistor has a current direction opposite a second body diode of the second transistor. When a display device powers up but a motherboard powers downs, a first control circuit turns on the first transistor and a second control circuit turns off the second transistor such that a current does not leak from the display power toward the first motherboard power due to the second body diode. When the display device powers down but the motherboard powers up, the first control circuit turns off the first transistor and the second control circuit turns off the second transistor such that the first motherboard power is not outputted to a video display interface due to the first body diode.

First claim

What is claimed is:

1. A display interface circuit, comprising:
a first transistor having a first body diode;
a second transistor having a second body diode, the first transistor and the second transistor being electrically connected in series between a first motherboard power and a display power, and the first body diode having a current direction opposite the second body diode;
a first control circuit that controls the first transistor; and
a second control circuit that controls the second transistor;
wherein when a display device powers up but a motherboard powers down, the first control circuit turns on the first transistor and the second control circuit turns off the second transistor, such that a current does not leak from the display power toward the first motherboard power due to the second body diode;
wherein when the display device powers down but the motherboard powers up, the first control circuit turns off the first transistor and the second control circuit turns off the second transistor, such that the first motherboard power is not outputted to a video display interface due to the first body diode, thus saving power;
wherein the first control circuit comprises a third transistor that is controlled by a hot plug signal, and accordingly generates a first control signal that controls the first transistor; and
wherein the second control circuit comprises a fourth transistor that is controlled by the first control signal and a second motherboard power, and accordingly generates a second control signal that controls the second transistor.

2. The display interface circuit of claim 1 , wherein the first transistor has a channel of first type and the second transistor has a channel of second type, and the first type is opposite the second type.

3. The display interface circuit of claim 2 , wherein the first transistor has a P-type channel and the second transistor has an N-type channel, and a source of the first transistor is connected to a drain of the second transistor.

4. The display interface circuit of claim 1 , wherein the video display interface comprises digital visual interface.

5. The display interface circuit of claim 1 , further comprising:
an inductor electrically connected in series to the first transistor and the second transistor; and
a fuse electrically connected in series to the first transistor and the second transistor.

6. The display interface circuit of claim 1 , wherein the first control circuit comprises:
the third transistor having a gate coupled to receive the hot plug signal from the video display interface, a source connected to ground, and a drain generating the first control signal to control the first transistor; and
a first resistor connected between the drain of the third transistor and the second motherboard power.

7. The display interface circuit of claim 6 , further comprising two Schottky diodes that are inversely connected between the gate and the source of the third transistor.

8. The display interface circuit of claim 6 , further comprising two Schottky diodes that are inversely connected between a pin associated with the hot plug signal and ground.

9. The display interface circuit of claim 1 , wherein the second control circuit comprises:
the fourth transistor having a gate coupled to receive an output of the first control circuit, a source connected to ground, and a drain generating the second control signal to control the second transistor; and
a second resistor connected between the drain of the fourth transistor and the second motherboard power.

10. The display interface circuit of claim 9 , further comprising two Schottky diodes that are inversely connected between the gate and the source of the fourth transistor.

11. A display interface method, comprising:
electrically connecting a first transistor and a second transistor in series between a first motherboard power and a display power, the first transistor having a first body diode with a current direction opposite a second body diode of the second transistor;
providing a first control circuit that controls the first transistor; and
providing a second control circuit that controls the second transistor;
wherein when a display device powers up but a motherboard powers down, the first control circuit turns on the first transistor and the second control circuit turns off the second transistor such that a current does not leak from the display power toward the first motherboard power due to the second body diode;
wherein when the display device powers down but the motherboard powers up, the first control circuit turns off the first transistor and the second control circuit turns off the second transistor such that the first motherboard power is not outputted to a video display interface due to the first body diode, thus saving power;
wherein the first control circuit comprises a third transistor that is controlled by a hot plug signal, and accordingly generates a first control signal that controls the first transistor; and
wherein the second control circuit comprises a fourth transistor that is controlled by the first control signal and a second motherboard power, and accordingly generates a second control signal that controls the second transistor.

12. The display interface method of claim 1 , wherein the first transistor has a channel of first type and the second transistor has a channel of second type, and the first type is opposite the second type.

13. The display interface method of claim 12 , wherein the first transistor has a P-type channel and the second transistor has an N-type channel, and a source of the first transistor is connected to a drain of the second transistor.

14. The display interface method of claim 11 , wherein the video display interface comprises digital visual interface.

15. A computer system, comprising:
a video display interface;
a display device;
a motherboard providing video signals to the display device via the video display interface; and
a system power generator providing a first motherboard power;
wherein the motherboard comprises a display interface circuit that comprises:
a first transistor having a first body diode;
a second transistor having a second body diode, the first transistor and the second transistor being electrically connected in series between the first motherboard power and a display power, and the first body diode having a current direction opposite the second body diode;
a first control circuit that controls the first transistor; and
a second control circuit that controls the second transistor;
wherein when the display device powers up but the motherboard powers down, the first control circuit turns on the first transistor and the second control circuit turns off the second transistor such that a current does not leak from the display power toward the first motherboard power due to the second body diode;
wherein when the display device powers down but the motherboard powers up, the first control circuit turns off the first transistor and the second control circuit turns off the second transistor such that the first motherboard power is not outputted to the video display interface due to the first body diode, thus saving power;

wherein the first control circuit comprises a third transistor that is controlled by a hot plug signal, and accordingly generates a first control signal that controls the first transistor; and
wherein the second control circuit comprises a fourth transistor that is controlled by the first control signal and a second motherboard power, and accordingly generates a second control signal that controls the se

Assignees

• Wistron Corp

Inventors

• Yang Ke
• Liao wei liang

Classifications

• G09G2330/027

  Arrangements or methods related to powering off a display · CPC title

• G09G3/2096 Primary

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2330/04

  Display protection · CPC title