Neuromorphic arithmetic device

Patent metadata

Field	Value
Publication number	US-10438116-B2
Application number	US-201715804912-A
Country	US
Kind code	B2
Filing date	Nov 6, 2017
Priority date	Feb 10, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

First claim

What is claimed is:

1. A neuromorphic arithmetic device comprising:
a first synapse circuit configured to generate a first current by performing a first multiplication operation on a first pulse width modulation (PWM) signal and a first weight;
a second synapse circuit configured to generate a second current by performing a second multiplication operation on a second PWM signal and a second weight;
a charging/discharging circuit configured to store charges induced by the first current and the second current in a charging period, and discharge the charges in a discharging period;
a comparator configured to compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage and output an enable signal which is activated in a period during which the voltage level of the discharged charges is higher than the reference voltage; and
a counter configured to count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

2. The neuromorphic arithmetic device of claim 1 , further comprising:
a first PWM converter configured to convert a first input into the first PWM signal; and
a second PWM converter configured to convert a second input into the second PWM signal.

3. The neuromorphic arithmetic device of claim 1 ,
wherein the first synapse circuit comprises:
a first AND gate configured to perform an AND operation on the first PWM signal and the first weight; and
a first charging current source configured to generate the first current according to an output from the first AND gate, and
wherein the second synapse circuit comprises:
a second AND gate configured to perform an AND operation on the second PWM signal and the second weight; and
a second charging current source configured to generate the second current according to an output from the second AND gate.

4. The neuromorphic arithmetic device of claim 3 ,
wherein the first charging current is configured so that a voltage level of the charging/discharging circuit induced by the first current increases linearly, and
wherein the second charging current is configured so that a voltage level of the charging/discharging circuit induced by the second current increases linearly.

5. The neuromorphic arithmetic device of claim 1 , wherein the charging/discharging circuit comprises:
a capacitor configured to store the charges in the charging period; and
a discharging current source configured to linearly decrease a voltage level of the capacitor induced by the charges in the discharging period.

6. The neuromorphic arithmetic device of claim 1 , wherein the comparator is a differential amplifier operating in a period during which the charging/discharging circuit is discharged.

7. The neuromorphic arithmetic device of claim 6 , wherein the counter counts the output pulses of the oscillator in a period during which the enable signal is activated.

8. The neuromorphic arithmetic device of claim 7 , further comprising a switch configured to be switched on in response to activation of the enable signal to connect the oscillator to the counter.

9. The neuromorphic arithmetic device of claim 7 , further comprising a switch disposed between the oscillator and the counter and receiving the enable signal, the switch transmitting the output pulses of the oscillator to the counter in the period during which the voltage level of the discharged charges is higher than the reference voltage.

10. The neuromorphic arithmetic device of claim 1 , wherein the first synapse circuit and the second synapse circuit share the oscillator that is a global oscillator.

11. The neuromorphic arithmetic device of claim 1 , wherein the counter counts a number of the output pulses of the oscillator in the period during which the voltage level of the discharged charges is higher than the reference voltage.

12. A neuromorphic arithmetic device comprising:
a first synapse circuit configured to generate a first current by performing a first multiplication operation on a first pulse width modulation (PWM) signal and a first weight;
a second synapse circuit configured to generate a second current by performing a second multiplication operation on a second PWM signal and a second weight;
a charging/discharging circuit configured to store charges induced by the first current and the second current in a charging period, and discharge the charges in a discharging period;
a comparator configured to compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage;
a counter configured to count output pulses of an oscillator on the basis of a result of the comparison by the comparator; and
a level shifter configured to shift a digital value output from the counter.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Oh Kwang Il
• Kim Sung Eun
• Park Seong Mo
• Park Hyung-Il
• Lee Jae-Jin
• Lee Joo Hyun

Classifications

• G06N3/065 Primary

  Analogue means · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F5/01

  for shifting, e.g. justifying, scaling, normalising {(digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00)} · CPC title

• G06F7/68

  using pulse rate multipliers or dividers {pulse rate multipliers or dividers per se}(G06F7/70 takes precedence {; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00}) · CPC title

• G06N3/0635 Primary

  Physics · mapped topic